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altera corporation section i?1 preliminary section i. max ii device family data sheet this section provides designers with the data sheet specifications for max ? ii devices. the chapters contain feature definitions of the internal architecture, joint test acti on group (jtag) and in-system programmability (isp) info rmation, dc operating conditions, ac timing parameters, and ordering information for max ii devices. this section includes the following chapters: chapter 1. introduction chapter 2. max ii architecture chapter 3. jtag & in-s ystem programmability chapter 4. hot socketing & power- on reset in max ii devices chapter 5. dc & switching characteristics chapter 6. reference & ordering information revision history the table below shows th e revision history for chapters 1 through 6 . chapter(s) date/version changes made 1 august 2006, v1.5 minor update to features list. july 2006, v1.4 minor updates to tables. june 2005, v1.3 updated timing numbers in table 1-1. december 2004, v1.2 updated timing numbers in table 1-1. june 2004, v1.1 updated timing numbers in table 1-1. 2 august 2006, v1.6 updated functional description and i/o structure sections.
section i?2 altera corporation preliminary revision history max ii device handbook july 2006, v1.5 minor content and table updates. february 2006, v1.4 updated ?lab control signals? section. updated ?clear & preset logic control? section. updated ?internal oscillator? section. updated table 2?5 . august 2005, v1.3 removed note 2 from table 2-7. december 2004, v1.2 added a paragraph to page 2-15. june 2004, v1.1 added cfm acronym. corrected figure 2-19. 3 june 2005, v1.3 added text and table 3-4. december 2004, v1.2 updated text on pages 3-5 to 3-8. june 2004, v1.1 corrected figure 3-1. added cfm acronym. 4 february 2006, v1.4 updated ?max ii hot-socketing specifications? section. updated ?ac & dc specifications? section. updated ?power-on reset circuitry? section. june 2005, v1.3 updated ac and dc specifications on page 4-2. december 2004, v1.2 added content to power-up characteristics section. updated figure 4-5. june 2004, v1.1 corrected figure 4-2. 5 july 2006, v. 1.7 minor content and table updates. february 2006, v1.6 updated ?external timing i/o delay adders? section. updated table 5?29 . updated table 5?30 . november 2005, v1.5 updated tables 5-2, 5-4, and 5-12. august 2005, v1.4 updated figure 5-1. updated tables 5-13, 5-16, and 5-26. removed note 1 from table 5-12. chapter(s) date/version changes made
altera corporation i?3 preliminary revision history june 2005, v1.3 updated the r pullup parameter in table 5-4. added note 2 to tables 5-8 and 5-9. updated table 5-13. added output drive characteristics section. added i 2 c mode and notes 5 and 6 to table 5-14. updated timing values to tables 5-14 through 5-33. december 2004, v1.2 updated timing tables 5-2, 5-4, 5-12, and tables 15-14 through 5-34. table 5-31 is new. june 2004, v1.1 updated timing tables 5-15 through 5-32. 6 june 2005, v1.1 removed dual marking section. chapter(s) date/version changes made
i?4 altera corporation preliminary revision history max ii device handbook
altera corporation core version a.b.c variable 1?1 august 2006 preliminary chapter 1. introduction introduction the max ? ii family of instant-on, non-volatile cplds is based on a 0.18-m, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (les) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 kbits. max ii devi ces offer high i/o counts, fast performance, and reliable fitting versus other cpld architectures. featuring multivolt? core, a user flash memory (u fm) block, and enhanced in-system programmability (i sp), max ii devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, i/o expansion, powe r-on reset (por) and sequencing control, and device configuration control. the following shows the main sections of the max ii cpld family data sheet: section page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 logic array blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 logic elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?8 multitrack interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 global signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?20 user flash memory block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?23 multivolt core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?27 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?28 ieee std. 1149.1 (jtag) boundary scan support . . . . . . . . . . 3?1 in system programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4 hot socketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 power-on reset circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?6 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?9 timing model & specifications . . . . . . . . . . . . . . . . . . . . . . . . 5?10 device pin-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1 mii51001-1.5
1?2 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 features features low-cost, low-power cpld instant-on, non-volatile architecture standby current as low as 2 ma provides fast propagation delay and clock-to-output times provides four global clocks with two clocks available per logic array block (lab) ufm block up to 8 kbits for non-volatile storage multivolt core enabling external supply voltages to the device of either 3.3 v/2.5 v or 1.8 v multivolt i/o interface supporting 3.3-v, 2.5-v, 1.8-v, and 1.5-v logic levels bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors schmitt triggers enabling noise tolerant inputs (programmable per pin) fully compliant with the peripheral component interconnect special interest group (pci sig) pci local bus specification, revision 2.2 for 3.3-v operation at 66 mhz supports hot-socketing built-in joint test action grou p (jtag) boundary-scan test (bst) circuitry compliant with ieee std. 1149.1-1990 isp circuitry complian t with ieee std. 1532 table 1?1 shows max ii device features. table 1?1. max ii device features feature epm240 epm570 epm1270 epm2210 les 240 570 1,270 2,210 typical equivalent macrocells 192 440 980 1,700 equivalent macrocell range 128 to 240 240 to 570 570 to 1,270 1,270 to 2,210 ufm size (bits) 8,192 8,192 8,192 8,192 maximum user i/o pins 80 160 212 272 t pd1 (ns) (1) 4.7 5.4 6.2 7.0 f cnt (mhz) (2) 304 304 304 304 t su (ns) 1.7 1.2 1.2 1.2 t co (ns) 4.3 4.5 4.6 4.6 notes to ta b l e 1 ? 1 : (1) t pd1 represents a pin-to-pin delay for the worst case i/o placement with a full diagonal path across the device and combinational logic implemented in a single lu t and lab that is adjacent to the output pin. (2) the maximum frequency is limited by the i/o standard on the clock input pi n. the 16-bit counter critical delay will run faster than this number.
altera corporation core version a.b.c variable 1?3 august 2006 max ii device handbook, volume 1 introduction 1 for more information on equivalent macrocells, refer to the max ii logic element to macrocell conversion methodology white paper. max ii devices are available in three sp eed grades: -3, -4, -5 with -3 being the fastest. these speed grades repr esent overall relative performance, not any specific timing parameter. for propagation delay timing numbers within each speed grade and density, see the chapter on dc & switching characteristics . table 1?2 shows max ii device speed-grade offerings. max ii devices are available in space-saving fineline bga ? , micro fineline bga, and thin quad fl at pack (tqfp) packages (see tables 1?3 and 1?4 ). max ii devices support vertic al migration within the same package (e.g., you can migrate between the epm570, epm1270, and epm2210 devices in the 256-pin fineline bga package). vertic al migration means that you can migrate to devices whose dedicated pins and jtag pins are the same and power pins are subsets or supersets for a given package across device densities. the largest density in an y package has the highest number of power pins; you must layout for the largest planned density in a package to provide the necessary power pins for migration. for i/o pin migration across densities, cross reference the available i/o pins using the device pin-outs for all planned densities of a given package type to identify which i/o pins can be migrated. the quartus ? ii software can automatically cross reference and pl ace all pins for you when given a device migration list. table 1?2. max ii speed grades device speed grade -3 -4 -5 epm240 vvv epm570 vvv epm1270 vvv epm2210 vvv
1?4 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 features table 1?3. max ii pack ages & user i/o pins device 100-pin micro fineline bga (1) 100-pin fineline bga (1) 100-pin tqfp 144-pin tqfp 256-pin micro fineline bga (1) 256-pin fineline bga 324-pin fineline bga epm240 80 80 80 epm570 76 76 76 116 160 160 epm1270 116 212 212 epm2210 204 272 note to ta b l e 1 ? 3 : (1) packages available on 3.3 v/2.5 v devices in lead-free versions only. table 1?4. max ii tqfp, fineline bga, & micro fi neline bga package sizes package 100-pin micro fineline bga 100-pin fineline bga 100-pin tqfp 144-pin tqfp 256-pin micro fineline bga 256-pin fineline bga 324-pin fineline bga pitch (mm) 0.5 1 0.5 0.5 0.5 1 1 area (mm2) 36 121 256 484 121 289 361 length x width (mm x mm) 6 x 6 11 x 11 16 16 22 22 11 x 11 17 17 19 19
altera corporation core version a.b.c variable 1?5 august 2006 max ii device handbook, volume 1 introduction max ii devices have an internal li near voltage regulator which supports external supply voltages of 3.3 v or 2.5 v, regulating the supply down to the internal operating voltage of 1.8 v. max iig devices only accept 1.8 v as an external supply voltage. ex cept for external supply voltage requirements, max ii and max ii g de vices have identical pin-outs and timing specifications. table 1?5 shows the external supply voltages supported by the max ii family. table 1?5. max ii external supply voltages devices epm240 epm570 epm1270 epm2210 epm240g epm570g epm1270g epm2210g (1) multivolt core external supply voltage (v ccint ) (2) 3.3 v, 2.5 v 1.8 v multivolt i/o interface voltage levels (v ccio ) 1.5 v, 1.8 v, 2.5 v, 3.3 v 1.5 v, 1.8 v, 2.5 v, 3.3 v notes to ta b l e 1 ? 5 : (1) max iig devices do not have an internal voltage regulator and only accept 1.8 v on their vccint pins. contact altera for availability on these devices. (2) max ii devices operate internally at 1.8 v.
1?6 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 features
altera corporation core version a.b.c variable 2?1 august 2006 preliminary chapter 2. max ii architecture functional description max ? ii devices contain a two-dimensional row- and column-based architecture to implement custom lo gic. column and row interconnect provide signal interconnects betwee n the logic array blocks (labs). the logic array consists of labs, wi th 10 logic elements (les) in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. the multitrack? interconnect provides fast granular timing delays between labs. the fast routing between les provides minimum timing delay for added levels of logic versus globally routed interconnect structures. the max ii device i/o pins are fed by an i/o element (ioe) located at the ends of lab rows and columns ar ound the periphery of the device. each ioe contains a bidirectional i/o buffer with several advanced features. i/o pins su pport schmitt trigger inputs and various single-ended standards, such as 66-mhz, 32-bit pci and lvttl. max ii devices provide a global cloc k network. the global clock network consists of four global clock lines th at drive throughout the entire device, providing clocks for all resources with in the device. the global clock lines can also be used for control signals such as clear, preset, or output enable. figure 2?1 shows a functional block di agram of the max ii device. mii51002-1.6
2?2 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 figure 2?1. max ii device block diagram each max ii device contains a flash memory block within its floorplan. on the epm240 device, this block is located on the le ft side of the device. for the epm570, epm1270, and ep m2210 devices, the flash memory block is located on the bottom-left area of the device. the majority of this flash memory storage is partitioned as the dedicated configuration flash memory (cfm) block. the cfm block provides the non-volatile storage for all of the sram configuration information. the cfm automatically downloads and configures the logi c and i/o at power-up providing instant-on operation. f see hot socketing & power-on reset in max ii devices for more information on configuration upon power-up. a portion of the flash memory within the max ii device is partitioned into a small block for user data. th is user flash memory (ufm) block provides 8,192 bits of general-purp ose user storage. the ufm provides programmable port connections to th e logic array for reading and for writing. there are three lab rows ad jacent to this bloc k, with column numbers varying by device. logic array block (lab ) multitrack interconnect multitrack interconnect logic element logic element ioe ioe ioe ioe logic element logic element ioe ioe logic element logic element ioe ioe logic element logic element logic element logic element ioe ioe logic element logic element
altera corporation core version a.b.c variable 2?3 august 2006 max ii device handbook, volume 1 max ii architecture table 2?1 shows the number of lab rows and columns in each device as well as the number of lab rows and columns adjacent to the flash memory area in the epm570, epm127 0, and epm2210 devices. the long lab rows are full lab rows that exte nd from one side of row i/o blocks to the other. the short lab rows are adjacent to the ufm block; their length is shown as width in lab columns. table 2?1. max ii device resources devices ufm blocks lab columns lab rows total labs long lab rows short lab rows (width) (1) epm240 1 6 4 - 24 epm570 1 12 4 3 (3) 57 epm1270 1 16 7 3 (5) 127 epm2210 1 20 10 3 (7) 221 note to ta b l e 2 ? 1 : (1) the width is the number of lab columns in length.
2?4 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 figure 2?2 shows a floorplan of a max ii device. figure 2?2. max ii device floorplan note (1) note to figure 2?2 : (1) the device shown is an epm570 device. epm1270 and epm2210 devices have a similar floorplan with more labs. for the epm240 devices, the cfm and ufm block is rotated left 90 degrees covering the left side of the device. ufm block cfm block i/o blocks logic array blocks i/o blocks logic arra y blocks 2 gclk inputs 2 gclk inputs i/o blocks
altera corporation core version a.b.c variable 2?5 august 2006 max ii device handbook, volume 1 max ii architecture logic array blocks each lab consists of 10 les, le carry chains, lab control signals, a local interconnect, a look-up table (lut) chain, and register chain connection lines. there are 26 possible unique inpu ts into an lab, with an additional 10 local feedback input lines fed by le outputs in the same lab. the local interconnect transfers signals between les in the same lab. lut chain connections transfer the output of one le?s lut to the adjacent le for fast sequential lut connections within the same lab. register chain connections transfer the ou tput of one le?s register to the adjacent le?s register within an lab. the quartus ? ii software places associated logic within an lab or adjacent labs, allowing the use of local, lut chain, and register chain connections for performance and area efficiency. figure 2?3 shows the max ii lab. figure 2?3. max ii lab structure note to figure 2?3 : (1) only from labs adjacent to ioes. directlink interconnect from adjacent lab or ioe directlink interconnect to adjacent lab or ioe row interconnect column interconnect local interconnect lab directlink interconnect from adjacent lab or ioe directlink interconnect to adjacent lab or ioe fast i/o connection to ioe (1) fast i/o connection to ioe (1) le0 le1 le2 le3 le4 le6 le7 le8 le9 le5 logic element
2?6 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 logic array blocks lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. neighb oring labs, from the left and right can also drive an lab?s local interconnect through the directlink connection. the directlink connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. each le can drive 30 other les through fast local and directlink interconnects. figure 2?4 shows the directlink connection. figure 2?4. directlink connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include two clocks, two clock enables, two asynchronous clears, a synchronous cl ear, an asynchronous preset/load, a synchronous load, and add/subtra ct control signals, providing a maximum of 10 control signals at a ti me. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. lab directlink interconnect to right directlink interconnect from right lab or ioe output directlink interconnect from left lab or ioe output local interconnect directlink interconnect to left le0 le1 le2 le3 le4 le6 le7 le8 le9 le5 logic element
altera corporation core version a.b.c variable 2?7 august 2006 max ii device handbook, volume 1 max ii architecture each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling ed ges of a clock, it also uses both lab-wide clock signals. de-asserting the clock enable signal turns off the lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous load /preset signal. by default, the quartus ii software uses a not gate push-back technique to achieve preset. if you disable the not gate push-back option or assign a given register to power-up high using the quartus ii software, the preset is th en achieved using the asynchronous load signal with as ynchronous load data input tied high. with the lab-wide addnsub control signal, a single le can implement a one-bit adder and subtractor. this saves le resources and improves performance for logic functions such as correlators and signed multipliers that alternate between addition and subtraction depending on data. the lab column clocks [3..0], driven by the global clock network, and lab local interconnect generate the lab-wide control signals. the multitrack tm interconnect structure drives the lab local interconnect for non-global control sign al generation. the multitrack interconnect?s inherent low skew allows clock and control signal distribution in addition to data. figure 2?5 shows the lab control signal generation circuit. figure 2?5. lab-wide control signals labclkena1 labclk2 labclk1 labclkena2 asyncload or labpre syncload dedicated lab column clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclr1 labclr2 synclr addnsub 4
2?8 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 logic elements logic elements the smallest unit of logic in the ma x ii architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le contains a four-input lut, which is a function generator that can implement any function of four variable s. in addition, each le contains a programmable register and carry chain with carry select capability. a single le also supports dynamic single bit addition or subtraction mode selectable by an lab-wide control signal. each le drives all types of interconnects: local, row, column, lut chain, register chain, and directlink interconnects. see figure 2?6 . figure 2?6. max ii le each le?s programmable register can be configured for d, t, jk, or sr operation. each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. global signals, general-purpose i/o pins, or any le can drive the register?s clock and clear control signals. either general- purpose i/o pins or les can drive the clock enable, preset, asynchronous load, and asynchronous data. the labclk1 labclk2 labclr2 labpre/aload carry-in1 carry-in0 lab carry-in clock & clock enable select lab carr y -out carry-out1 carry-out0 look-up ta b l e (lut) carry chain row, column, and directlink routing row, column, and directlink routing programmable register prn/ald clrn d q ena register bypass packed register select chip-wide reset (dev_clrn) labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load logic data1 data2 data3 data4 lut chain routing to next le labclr1 local routing register chain output a data addnsub register feedback register chain routing from previous le
altera corporation core version a.b.c variable 2?9 august 2006 max ii device handbook, volume 1 max ii architecture asynchronous load data input comes from the data3 input of the le. for combinational functions, the lut output bypasses the register and drives directly to the le outputs. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and directlink routing connections and one drives local interconnect resources. this allows the lut to drive one output while the register drives another output. this register packing feature improves device utilization because the device can use the register an d the lut for unrelated functions. another special packing mode allows the register output to feed back into the lut of the same le so that the re gister is packed with its own fan-out lut. this provides another mechanism for improved fitting. the le can also drive out registered and unregi stered versions of the lut output. lut chain & register chain in addition to the three general routing outputs, the les within an lab have lut chain and register chain ou tputs. lut chain connections allow luts within the same lab to cascad e together for wide input functions. register chain outputs allow register s within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinational function and the register s to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local in terconnect resources. see ?multitrack interconnect? on page 2?15 for more information on lut chain and register chain connections. addnsub signal the le?s dynamic adder/subtractor feature saves logic resources by using one set of les to implement both an adder and a subtractor. this feature is controlled by the lab-wide control signal addnsub . the addnsub signal sets the lab to perform either a + b or a ? b. the lut computes addition; subtraction is computed by adding the two?s complement of the intended subtractor . the lab-wide signal converts to two?s complement by inverting the b bits within the lab and setting carry-in to 1, which adds one to the least significant bit (lsb). the lsb of an adder/subtractor must be placed in the first le of the lab, where the lab-wide addnsub signal automatic ally sets the carry-in to 1. the quartus ii compiler autom atically places and uses the adder/subtractor feature when using adder/subtra ctor parameterized functions.
2?10 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 logic elements le operating modes the max ii le can operate in one of the following modes: normal mode dynamic arithmetic mode each mode uses le resources differently. in each mode, eight available inputs to the le, the four data inpu ts from the lab local interconnect, carry-in0 and carry-in1 from the previous le, the lab carry-in from the previous carry-chain lab, and the register chain connection are directed to different destinations to implement the desire d logic function. lab-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes. the addnsub control signal is allowed in arithmetic mode. the quartus ii software, in conjun ction with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. normal mode the normal mode is suitable for general logic applications and combinational functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?7 ). the quartus ii compiler automatica lly selects the carry-in or the data3 signal as one of the inputs to th e lut. each le can use lut chain connections to drive its combinational output directly to the next le in the lab. asynchronous load data for the register comes from the data3 input of the le. les in normal mode support packed registers.
altera corporation core version a.b.c variable 2?11 august 2006 max ii device handbook, volume 1 max ii architecture figure 2?7. le in normal mode note to figure 2?7 : (1) this signal is only allowed in normal mode if the le is at the end of an adder/subtractor chain. dynamic arithmetic mode the dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. an le in dynamic arithmetic mode uses four 2-input luts configurable as a dynamic adder/subtractor. the first two 2-input luts compute two summations based on a possible carry-in of 1 or 0; the other two luts generate carry outputs for the two chains of the ca rry select circuitry. as shown in figure 2?8 , the lab carry-in signal selects either the carry-in0 or carry-in1 chain. the selected chain?s logic level in turn determines which parallel sum is generated as a combinational or registered output. for example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry in0 or data1 + data2 + carry-in1 data1 4-input lut data2 data3 cin (from cout of previous le) data4 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) aload (lab wide) ald/pre clrn d q ena a data sclear (lab wide) sload (lab wide) register chain connection lut chain connection register chain output row, column, and directlink routing row, column, and directlink routing local routing register feedback (1)
2?12 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 logic elements the other two luts use the data1 and data2 signals to generate two possible carry-out signals: one for a ca rry of 1 and the other for a carry of 0. the carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the dynamic arithmetic mode also of fers clock enable, counter enable, synchronous up/down control, sync hronous clear, sy nchronous load, and dynamic adder/subtrac tor options. the lab local interconnect data inputs generate the counter enable and synchronous up/down control signals. the synchronous clear and synchronous load options are lab-wide signals that affect all registers in the lab. the quartus ii software automatically places any re gisters that are not used by the counter into other labs. the addnsub lab-wide signal controls whether the le acts as an adder or subtractor. figure 2?8. le in dynamic arithmetic mode note to figure 2?8 : (1) the addnsub signal is tied to the carry input for the first le of a carry chain only. data1 lut data2 data3 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) ald/pre clrn d q ena a data register chain connection lut lut lut carry-out1 carry-out0 lab carry-in carry-in0 carry-in1 (1) sclear (lab wide) sload (lab wide) lut chain connection register chain output row, column, an d direct link routing row, column, an d direct link routing local routing aload (lab wide) register feedback
altera corporation core version a.b.c variable 2?13 august 2006 max ii device handbook, volume 1 max ii architecture carry-select chain the carry-select chain provides a very fast carry-select function between les in dynamic arithmetic mode. the carry-select chain uses the redundant carry calculation to increase the speed of carry functions. the le is configured to calculate outputs for a possible carry-in of 0 and carry-in of 1 in parallel. the carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the lu t and the next portion of the carry chain. carry-select chains can be gin in any le within an lab. the speed advantage of the carry-select chain is in the parallel pre-computation of carry chains. since the lab carry-in selects the precomputed carry ch ain, not every le is in th e critical path. only the propagation delays between lab carry-in generation (le 5 and le 10) are now part of the critical path. this fe ature allows the max ii architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. figure 2?9 shows the carry-select circuitry in an lab for a 10-bit full adder. one portion of the lut generates the sum of two bits using the input signals and the appr opriate carry-in bit; the sum is routed to the output of the le. the register can be bypassed for simple adders or used for accumulator functions. another portion of the lut generates carry-out bits. an lab-wide carry-in bit selects which chain is used for the addition of given inputs. the carry-in signal for each chain, carry-in0 or carry-in1 , selects the carry-out to carry forward to the carry-in signal of the next-higher-orde r bit. the final carry-out signal is routed to an le, where it is fed to local, row, or column interconnects.
2?14 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 logic elements figure 2?9. carry select chain the quartus ii software automatically creates carry chain logic during design processing, or the designer ca n create it manually during design entry. parameterized functions such as lpm functions au tomatically take advantage of carry chains for the a ppropriate functions. the quartus ii software creates carry chains longer than 10 les by linking adjacent labs within the same row together automa tically. a carry chain can extend horizontally up to one full lab row, but they do not extend between lab rows. le3 le2 le1 le0 a1 b1 a2 b2 a3 b3 a4 b4 sum1 sum2 sum3 sum4 le9 le8 le7 le6 a7 b7 a8 b8 a9 b9 a10 b10 sum7 le5 a6 b6 sum6 le4 a5 b5 sum5 sum8 sum9 sum10 01 01 lab carry-in lab carr y -out lut lut lut lut data1 lab carry-in data2 carry-in0 carry-in1 carry-out0 carry-out1 sum to top of adjacent lab
altera corporation core version a.b.c variable 2?15 august 2006 max ii device handbook, volume 1 max ii architecture clear & preset logic control lab-wide signals control the logic for the register?s clear and preset signals. the le directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynch ronous preset does not require a not-gate push-back tec hnique. max ii devices support simultaneous preset/asynchronous load and clear signals. an asynchronous clear signal takes precedence if both signals are asserted simultaneously. each lab supports up to two clears and one preset signal. in addition to the clear and preset ports, max ii devices provide a chip-wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the qu artus ii software controls this pin. this chip-wide reset overrides all other control signals and uses its own dedicated routing resources (i.e., it does not use any of the four global resources). driving this signal low before or during power-up prevents user mode from releasing clears within the design. this allows you to control when clear is released on a device that has just been powered-up. if not set for its chip-wide reset function, the dev_clrn pin is a regular i/o pin. by default, all registers in max ii devices are set to power-up low. however, this power-up state can be set to high on individual registers during design entry using the quartus ii software. multitrack interconnect in the max ii architecture, connect ions between les, the ufm, and device i/o pins are provided by the multitrack interconnect structure. the multitrack interconnect cons ists of continuous, performance- optimized routing lines used for inter- and intra-design block connectivity. the quartus ii compiler automatically places critical design paths on faster interconnects to improve design performance. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and short delays between logic levels instead of large delays associated with global or long routing lines. dedicated row interconnects route si gnals to and from labs within the same row. these row resources include: directlink interconnects between labs r4 interconnects traversing four labs to the right or left the directlink interconnect allows an lab to drive into the local interconnect of its left and right ne ighbors. the directlink interconnect provides fast communication betwee n adjacent labs and/or blocks without using row interconnect resources.
2?16 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 multitrack interconnect the r4 interconnects span four labs and are used for fast row connections in a four-lab region. every lab has its own set of r4 interconnects to drive either left or right. figure 2?10 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by row ioes. for lab interfacing, a primary lab or horizontal lab neighbor can drive a given r4 interconnect. for r4 interconnects that drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 in terconnects for connections from one row to another. figure 2?10. r4 interconnect connections notes to figure 2?10 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
altera corporation core version a.b.c variable 2?17 august 2006 max ii device handbook, volume 1 max ii architecture the column interconnect operates similarly to the row interconnect. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs and row and column ioes. these column resources include: lut chain interconne cts within an lab register chain intercon nects within an lab c4 interconnects traversing a distan ce of four labs in an up and down direction max ii devices include an enhanced interconnect structure within labs for routing le output to le input connections faster using lut chain connections and register chain conne ctions. the lut chain connection allows the combinational output of an le to directly drive the fast input of the le right below it, bypassing the local interconnect. these resources can be used as a high-speed connecti on for wide fan-in functions from le 1 to le 10 in the same lab. the register chain connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. the quartus ii compiler automatically takes advantage of th ese resources to improve utilization and performance. figure 2?11 shows the lut chain and register chain interconnects.
2?18 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 multitrack interconnect figure 2?11. lut chain & register chain interconnects the c4 interconnects span four labs up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?12 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by column and row ioes. for lab interconnection, a primary lab or its vertical lab neighbor can drive a given c4 interc onnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. le0 le1 le2 le3 le4 le5 le6 le7 le8 le9 lut chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab
altera corporation core version a.b.c variable 2?19 august 2006 max ii device handbook, volume 1 max ii architecture figure 2?12. c4 inte rconnect connections note (1) note to figure 2?12 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect
2?20 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 global signals the ufm block communicates with the logic array similar to lab-to-lab interfaces. the ufm block connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. this block also has directlink inte rconnects for fast connections to and from a neighboring lab. for more in formation on the ufm interface to the logic array, see ?user flash memory block? on page 2?23 . table 2?2 shows the max ii device's routing scheme. global signals each max ii device has four dual-purpose dedicated clock pins ( gclk[3..0] , two pins on the left side an d two pins on the right side) that drive the global clock netw ork for clocking, as shown in figure 2?13 . these four pins can also be used as general-purpose i/o if they are not used to drive the global clock network. the four global clock lines in the gl obal clock network drive throughout the entire device. the global clock network can provide clocks for all resources within the device including les, lab local interconnect, ioes, and the ufm block. the global clock lines can also be used for global table 2?2. max ii device routing scheme source destination lut chain register chain local (1) directlink (1) r4 (1) c4 (1) le ufm block column ioe row ioe fast i/o (1) lut chain v register chain v local interconnect vv v v directlink interconnect v r4 interconnect vvv c4 interconnect vvv le vvv v v v vvv ufm block vv vv column ioe v row ioe vvv note to ta b l e 2 ? 2 : (1) these categories are interconnects.
altera corporation core version a.b.c variable 2?21 august 2006 max ii device handbook, volume 1 max ii architecture control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, or protocol control signals such as trdy and irdy for pci. internal logic can dr ive the global clock network for internally- generated global clocks and control signals. figure 2?13 shows the various sources that driv e the global clock network. figure 2?13. global clock generation note to figure 2?13 : (1) any i/o pin can use a multitrack interconnect to route as a logic array-generated global clock signal. the global clock network drives to individual lab column signals, lab column clocks [3..0], that span an entire lab column from the top to bottom of the device. unused global clocks or control signals in a lab column are turned off at the lab column clock buffers shown in figure 2?14 . the lab column clocks [3..0] are multiplexed down to two lab clock signals and one lab clear signal. other control signal types route from the global clock network into the lab local interconnect. see ?lab control signals? on page 2?6 for more information. 4 4 gclk0 global clock network gclk1 gclk2 gclk3 logic array (1)
2?22 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 global signals figure 2?14. global clock network note (1) notes to figure 2?14 : (1) lab column clocks in i/o block regions provide high fan-out output enable signals. (2) lab column clocks drive to the ufm block. ufm block (2) cfm block i/o block region i/o block region i/o block region lab column clock[3..0] lab column clock[3..0] 4 4 4 4 4 4 4 4
altera corporation core version a.b.c variable 2?23 august 2006 max ii device handbook, volume 1 max ii architecture user flash memory block max ii devices feature a single ufm bloc k, which can be used like a serial eeprom for storing non-volatile information up to 8,192 bits. the ufm block connects to the logic array through the multitrack interconnect, allowing any le to interf ace to the ufm block. figure 2?15 shows the ufm block and interface signals. the logic array is used to create customer interface or protocol logi c to interface the ufm block data outside of the device. the ufm block offers the following features: non-volatile storage up to 16-bit wide and 8,192 total bits two sectors for partitioned sector erase built-in internal oscillator that optionally drives logic array program, erase, and busy signals auto-increment addressing serial interface to logic array with programmable interface figure 2?15. ufm block & interface signals osc 4 program erase control ufm sector 1 ufm sector 0 : _ address register program erase osc_ena rtp_busy busy osc data register ufm block drdin drdout arclk arshft ardin drclk drshft 16 16 9
2?24 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 user flash memory block ufm storage each device stores up to 8,192 bi ts of data in the ufm block. table 2?3 shows the data size, sector, and address sizes for the ufm block. there are 512 locations with 9-bit addressing ranging from 000h to 1ffh . sector 0 address space is 000h to 0ffh and sector 1 address space is from 100h to 1ffh . the data width is up to 16 bits of data. the quartus ii software automatically creates logi c to accommodate smaller read or program data widths. erasure of the ufm involves individual sector erasing (i.e., one erase of sector 0 and one erase of sector 1 is required to erase the entire ufm block). since se ctor erase is required before a program or write, having two sectors enables a sector size of data to be left untouched while the other sector is erased and programmed with new data. internal oscillator as shown in figure 2?15 , the dedicated circuitry within the ufm block contains an oscillator. the dedicated circuitry uses this internally for its read and program operations. this os cillator's divide by 4 output can drive out of the ufm block as a lo gic interface clock source or for general-purpose logic clocking. the osc output signal frequency ranges from 3.3 to 5.5 mhz, and its exac t frequency of operation is not programmable. program, erase & busy signals the ufm block?s dedicated circui try automatically generates the necessary internal program an d erase algorithm once the program or erase input signals have been asserted. the program or erase signal must be asserted until the busy signal deasserts, indicating the ufm internal program or erase operation has completed. the ufm block also supports jtag as the interface fo r programming and/or reading. f for more information on programmin g and erasing the ufm block, see the chapter on using user flash memory in max ii devices . table 2?3. ufm array size device total bits sectors address bits data width epm240 epm570 epm1270 epm2210 8,192 2 (4,096 bits/sector) 916
altera corporation core version a.b.c variable 2?25 august 2006 max ii device handbook, volume 1 max ii architecture auto-increment addressing the ufm block supports standard read or stream read operations. the stream read is supported with a auto-increment address feature. de-asserting the arshift signal while clocking the arclk signal increments the address register value to read consecutive locations from the ufm array. serial interface the ufm block supports a serial interf ace with serial address and data signals. the internal shift registers within the ufm block for address and data are 9 bits and 16 bits wide, re spectively. the quartus ii software automatically generates interface logic in les for a parallel address and data interface to the ufm block. othe r standard protocol interfaces such as spi are also automatically generated in le logic by the quartus ii software. f for more information on the ufm interface signals and the quartus ii le-based alternate interfaces, see using user flash memory in max ii devices . ufm block to logic array interface the ufm block is a small partition of the flash memory which contains the cfm block as shown in figures 2?1 and 2?2 . the ufm block for the epm240 device is located on the left si de of the device adjacent to the left most lab column. the ufm block for the epm570, epm1270, and epm2210 devices is located on the bottom left portion of the device. the ufm input and output signals interface to all types of interconnects (r4 interconnect, c4 interconnect, and directlink interconnect to/from adjacent lab rows). the ufm signals can also be driven from global clocks, gclk[3..0] . the interface region for the epm240 device is shown in figure 2?16 . the interface regions for epm570, epm1270, and epm2210 devices are shown in figure 2?17 .
2?26 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 user flash memory block figure 2?16. epm240 ufm block lab row interface note (1) note to figure 2?16 : (1) the ufm block inputs and outputs can drive to/from all types of interconnects, not only directlink interconnects from adjacent row labs. ufm block cfm block program erase osc_ena drdin drclk drshft arin arclk arshft drdout osc busy rtp_busy lab lab lab
altera corporation core version a.b.c variable 2?27 august 2006 max ii device handbook, volume 1 max ii architecture figure 2?17. epm570, epm1270 & epm2210 ufm block lab row interface multivolt core the max ii architecture supports the multivolt tm core feature, which allows max ii devices to support multiple v cc levels on the v ccint supply. an internal linear voltage re gulator provides the necessary 1.8-v internal voltage supply to the device. the voltage regulator supports 3.3-v or 2.5-v supplies on its inputs to supply the 1.8-v internal voltage to the device, as shown in figure 2?18 . the voltage regulator is not guaranteed for voltages that are between the maximum recommended 2.5-v operating voltage and the mi nimum recommended 3.3-v operating voltage. for external 1.8-v suppl ies, max iig devices are required. the voltage regulator on these devices is bypassed to support the 1.8-v v cc external supply path to the 1.8-v internal supply. rtp_busy busy osc drdout drdin program erase osc_ena arclk arshft drdclk drdshft ardin ufm block cfm block lab lab lab
2?28 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure figure 2?18. multivolt core feature in max ii devices i/o structure ioes support many features, including: lvttl and lvcmos i/o standards 3.3-v, 32-bit, 66-mhz pci compliance joint test action group (jtag) boundary-scan test (bst) support programmable drive strength control weak pull-up resistors during power-up and in system programming slew-rate control tri-state buffers with individual output enable control bus-hold circuitry programmable pull-up resistors in user mode unique output enable per pin open-drain outputs schmitt trigger inputs fast i/o connection programmable input delay max ii device ioes contain a bidirectional i/o buffer. figure 2?19 shows the max ii ioe structure. registers fr om adjacent labs can drive to or be driven from the ioe?s bidirectional i/o buffers. the quartus ii software automatically attempts to place registers in the adjacent lab with fast i/o connection to achieve the fastest possible clock-to-output and registered output enable timing. for input registers, the quartus ii software automatically routes the regi ster to guarantee zero hold time. you can set timing assignments in the quartus ii software to achieve desired i/o timing. max ii device 3.3-v or 2.5-v on vccint pins voltage regulator 1.8-v core voltage max ii device with "g" ordering code 1.8-v on vccint pins 1.8-v core voltage
altera corporation core version a.b.c variable 2?29 august 2006 max ii device handbook, volume 1 max ii architecture fast i/o connection a dedicated fast i/o connection from the adjacent lab to the ioes within an i/o block provides faster output delays for clock-to-output and t pd propagation delays. this connection ex ists for data outp ut signals, not output enable signals or input signals. figures 2?20 , 2?21 , and 2?22 illustrate the fast i/o connection. figure 2?19. max ii ioe structure note to figure 2?19 : (1) available in epm1270 and epm2210 devices only. data_in optional schmitt trigger input drive strength control open-drain output slew control fast_out data_out oe optional pci clamp (1) programmable pull-up v ccio v ccio i/o pin optional bus-hold circuit dev_oe programmable input delay
2?30 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure i/o blocks the ioes are located in i/o blocks around the periphery of the max ii device. there are up to seven ioes per row i/o block (5 maximum in the epm240 device) and up to four ioes per column i/o block. each column or row i/o block interfaces with its adjacent lab and multitrack interconnect to distribute signals throughout the device. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?20 shows how a row i/o block connects to the logic array.
altera corporation core version a.b.c variable 2?31 august 2006 max ii device handbook, volume 1 max ii architecture figure 2?20. row i/o block c onnection to the interconnect note (1) note to figure 2?20 : (1) each of the seven ioes in the row i/o block can have one data_out or fast_out output, one oe output, and one data_in input. 7 r4 interconnects c4 interconnects i/o block local interconnect data_in[6..0] data_out [6..0] 7 oe [6..0] 7 7 fast_out [6..0] row i/o block contains up to seven ioes direct link interconnect to adjacent lab direct link interconnect from adjacent lab lab column clock [3..0] lab local interconnect lab row i/o block
2?32 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure figure 2?21 shows how a column i/o bloc k connects to th e logic array. figure 2?21. column i/o block connection to the interconnect note (1) note to figure 2?21 : (1) each of the four ioes in the column i/o block can have one data_out or fast_out output, one oe output, and one data_in input. column i/o block contains up to 4 ioes i/o block local interconnect r4 interconnects lab local interconnect c4 interconnects lab local interconnect c4 interconnects 4 lab lab lab data_out [3..0] 4 oe [3..0] 4 fast_out [3..0] fast i/o interconnect path 4 data_in [3..0] column i/o block lab local interconnect lab column clock [3..0]
altera corporation core version a.b.c variable 2?33 august 2006 max ii device handbook, volume 1 max ii architecture i/o standards & banks max ii device ioes support the following i/o standards: 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos 3.3-v pci table 2?4 describes the i/o standards supported by max ii devices. the epm240 and epm570 devices suppo rt two i/o banks, as shown in figure 2?22 . each of these banks support all the lvttl and lvcmos standards shown in table 2?4 . pci i/o is not supported in these devices and banks. table 2?4. max ii i/o standards i/o standard type output supply voltage (v ccio ) (v) 3.3-v lvttl/lvcmos single-ended 3.3 2.5-v lvttl/lvcmos single-ended 2.5 1.8-v lvttl/lvcmos single-ended 1.8 1.5-v lvcmos single-ended 1.5 3.3-v pci (1) single-ended 3.3 note to ta b l e 2 ? 4 : (1) 3.3-v pci is supported in bank 3 of the epm1270 and epm2210 devices.
2?34 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure figure 2?22. max ii i/o banks for epm240 & epm570 notes (1) , (2) notes to figure 2?22 : (1) figure 2?22 is a top view of the silicon die. (2) figure 2?22 is a graphic representation only. refer to the pin li st and the quartus ii softwa re for exact pin locations. the epm1270 and epm2210 devices support four i/o banks, as shown in figure 2?23 . each of these banks support all of the lvttl and lvcmos standards shown in table 2?4 . pci i/o is supported in bank 3. bank 3 supports the pci clamping diode on inputs and pci drive compliance on outputs. you must use bank 3 for designs requiring pci compliant i/o pins. the quartus ii softwa re automatically places i/o pins in this bank if assigned with the pci i/o standard. all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos i/o bank 2 i/o bank 1
altera corporation core version a.b.c variable 2?35 august 2006 max ii device handbook, volume 1 max ii architecture figure 2?23. max ii i/o banks for epm1270 & epm2210 notes (1) , (2) notes to figure 2?23 : (1) figure 2?23 is a top view of the silicon die. (2) figure 2?23 is a graphic representation only. refer to the pin li st and the quartus ii softwa re for exact pin locations. each i/o bank has dedicated vccio pins which determine the voltage standard support in that bank. a single device can support 1.5-v, 1.8-v, 2.5-v, and 3.3-v interfaces; each indi vidual bank can support a different standard. each i/o bank can support multiple standards with the same v ccio for input and output pins. for example, when v ccio is 3.3 v, bank 3 can support lvttl, lvcmos, and 3.3-v pci. v ccio powers both the input and output buffer s in max ii devices. the jtag pins for max ii devices are dedicated pins that cannot be used as regular i/o pins. the pins tms , tdi , tdo , and tck support all the i/o standards shown in table 2?4 on page 2?33 except for pci. these pins reside in bank 1 for all max ii devices and their i/o standard support is controlled by the v ccio setting for bank 1. i/o bank 2 i/o bank 3 i/o bank 4 i/o bank 1 all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos also support s the 3.3-v pci i/o standard
2?36 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure pci compliance max ii epm1270 and epm2210 devices are compliant with pci applications as well as all 3.3-v electrical specifications in the pci local bus specification revision 2.2 . these devices are also large enough to support pci intellectual property (ip) cores. table 2?5 shows the max ii device speed grades that meet the pci timing specifications. schmitt trigger the input buffer for each max ii devi ce i/o pin has an optional schmitt trigger setting for the 3.3-v and 2. 5-v standards. the schmitt trigger allows input buffers to respond to sl ow input edge rates with a fast output edge rate. most importantly, schmitt triggers provide hysteresis on the input buffer, preventing slow rising noisy input signals from ringing or oscillating on the input sign al driven into the logic array. this provides system noise tolerance on max ii inputs, bu t adds a small, nominal input delay. the jtag input pins ( tms , tck , and tdi ) have schmitt trigger buffers which are always enabled. output enable signals each max ii ioe output buffer supports output enable signals for tri-state control. the output enab le signal can originate from the gclk[3..0] global signals or from the multitrack interconnect. the multitrack interconnect routes outp ut enable signals and allows for a unique output enable for each output or bidirectional pin. table 2?5. max ii devices & speed grades that s upport 3.3-v pci electrical specifications & meet pci timing device 33-mhz pci 66-mhz pci epm1270 all speed grades -3 speed grade epm2210 all speed grades -3 speed grade
altera corporation core version a.b.c variable 2?37 august 2006 max ii device handbook, volume 1 max ii architecture max ii devices also provide a chip-wide output enable pin ( dev_oe ) to control the output enable for every ou tput pin in the design. an option set before compilation in the quartus ii software controls this pin. this chip-wide output enable uses its ow n routing resources and does not use any of the four global resources. if th is option is turned on, all outputs on the chip operate normally when dev_oe is asserted. when the pin is de-asserted, all outputs are tri-stated. if this option is turned off, the dev_oe pin is disabled when the device operates in user mode and is available as a user i/o pin. programmable drive strength the output buffer for each max ii device i/o pin has two levels of programmable drive strength control for each of the lvttl and lvcmos i/o standards. programmable drive strength provides system noise reduction control for high pe rformance i/o designs. although a separate slew-rate control feature exists, using the lower drive strength setting provides signal slew rate control to reduce system noise and signal overshoot without the large delay ad der associated with the slew-rate control feature. table 2?6 shows the possible settings for the i/o standards with drive strength control. the pci i/o standard is always set at 20 ma with no alternate setting. table 2?6. programmable drive strength note (1) i/o standard i oh /i ol current strength setting (ma) 3.3-v lvttl 16 8 3.3-v lvcmos 8 4 2.5-v lvttl/lvcmos 14 7 1.8-v lvttl/lvcmos 6 3 1.5-v lvcmos 4 2 note to ta b l e 2 ? 6 : (1) the i oh current strength numbers shown are for a condition of a v out = v oh minimum, where the v oh minimum is specified by the i/o standard. the i ol current strength numbers shown are for a condition of a v out = v ol maximum, where the v ol maximum is specified by the i/o standard. for 2.5-v lvttl/lvcmos, the i oh condition is v out = 1.7 v and the i ol condition is v out = 0.7 v.
2?38 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure slew-rate control the output buffer for each max ii device i/o pin has a programmable output slew-rate control that can be configured for low noise or high-speed performance. a faster slew rate provides high-speed transitions for high-performance system s. however, these fast transitions may introduce noise transients into th e system. a slow slew rate reduces system noise, but adds a nominal output delay to rising and falling edges. the lower the voltage standard (e.g., 1.8-v lvttl) the larger the output delay when slow slew is enabled. each i/o pin has an individual slew-rate control, allowing the designer to specify the slew rate on a pin-by-pin basis. the slew-rate contro l affects both the rising and falling edges. open-drain output max ii devices provide an option al open-drain (equivalent to open-collector) output for each i/o pi n. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. this output can also provide an additional wired-or plane. programmable ground pins each unused i/o pin on max ii devi ces can be used as an additional ground pin. this programmable ground feature does not require the use of the associated les in the device. in the quartus ii software, unused pins can be set as programmable gnd on a global default basis or they can be individually assigned. unused pins also have the option of being set as tri-stated input pins. bus hold each max ii device i/o pin provides an optional bus-ho ld feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. the designer can select this feature individually for each i/o pin. the bus-hold output will drive no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the device cannot use the programmable pull-up option.
altera corporation core version a.b.c variable 2?39 august 2006 max ii device handbook, volume 1 max ii architecture the bus-hold circuitry uses a resistor to pull the signal level to the last driven state. the chapter on dc & switching characteristics gives the specific sustaining current for each v ccio voltage level driven through this resistor and overdrive current us ed to identify the next-driven input level. the bus-hold circuitry is only active after the device has fully initialized. the bus-hold circuit captures the valu e on the pin present at the moment user mode is entered. programmable pull-up resistor each max ii device i/o pin provides an optional programmable pull-up resistor during user mode. if the designer enables this feature for an i/o pin, the pull-up resistor holds th e output to the v ccio level of the output pin?s bank. 1 the programmable pull-up resistor feature should not be used at the same time as the bus-hold feature on a given i/o pin. programmable input delay the max ii ioe includes a programmable input delay that is activated to ensure zero hold times. a path where a pin directly drives a register, with minimal routing between the two, ma y require the delay to ensure zero hold time. however, a path where a pin drives a register through long routing or through combinational logic may not require the delay to achieve a zero hold time . the quartus ii software uses this delay to ensure zero hold times when needed. multivolt i/o interface the max ii architecture supports th e multivolt i/o interface feature, which allows max ii devices in all packages to interface with systems of different supply voltages. the devices have one set of vcc pins for internal operation ( vccint ), and four sets for input buffers and i/o output driver buffers ( vccio ).
2?40 core version a.b.c variable altera corporation max ii device handbook, volume 1 august 2006 i/o structure connect vccio pins to either a 1.5-v, 1.8 v, 2.5-v, or 3.3-v power supply, depending on the output requirements. the output levels are compatible with systems of the same voltage as the power supply (i.e., when vccio pins are connected to a 1.5-v powe r supply, the output levels are compatible with 1.5-v systems). when vccio pins are connected to a 3.3-v power supply, the output high is 3.3 v and is compatible with 3.3-v or 5.0-v systems. table 2?7 summarizes max ii multivolt i/o support. table 2?7. max ii mu ltivolt i/o support note (1) v ccio (v) input signal output signal 1.5 v1.8 v2.5 v3.3 v5.0 v1.5 v1.8 v2.5 v3.3 v5.0 v 1.5 vvv v v 1.8 vvv v (2) v 2.5 vv v (3) v (3) v 3.3 v (4) vv (5) v (6) v (6) v (6) vv (7) notes to ta b l e 2 ? 7 : (1) to drive inputs higher than v ccio but less than 4.0 v including the oversh oot, disable the pci clamping diode. however, to drive 5.0-v inputs to the device , enable the pci clamping diode to prevent v i from rising above 4.0 v. (2) when v ccio = 1.8-v, a max ii device can drive a 1.5-v device with 1.8-v tolerant inputs. (3) when v ccio = 2.5-v, a max ii device can drive a 1.5-v or 1.8-v device with 2.5-v tolerant inputs. (4) when v ccio = 3.3-v and a 2.5-v input signal feeds an input pin, the vccio supply current will be slightly larger than expected. (5) max ii devices can be 5.0-v tolerant with the use of an external resistor and the inte rnal pci clamp diode on the epm1270 and epm2210 devices. (6) when v ccio = 3.3-v, a max ii device can drive a 1.5-v, 1.8- v, or 2.5-v device with 3.3-v tolerant inputs. (7) when v ccio = 3.3-v, a max ii device can drive a device with 5.0-v ttl inputs but not 5. 0-v cmos inputs. in the case of 5.0-v cmos, open-drain settin g with internal pci clamp diode (available only on epm1270 and epm2210 devices) and external resistor is required.
altera corporation core version a.b.c variable 3?1 june 2005 preliminary chapter 3. jtag & in-system programmability ieee std. 1149.1 (jtag) boundary scan support all max ? ii devices provide joint test action group (jtag) boundary- scan test (bst) circuitry that compli es with the ieee std. 1149.1-2001 specification. jtag boundary-scan testing can only be performed at any time after v ccint and all v ccio banks have been fully powered and a t config amount of time has passed. max ii devices can also use the jtag port for in-system programming tog ether with either the quartus ? ii software or hardware using programming object files ( .pof ), jam tm standard test and programming language (stapl) files ( .jam ) or jam byte-code files ( .jbc ). the jtag pins support 1.5-v, 1.8-v, 2.5-v, or 3.3-v i/o standards. the supported voltage level and standard is determined by the v ccio of the bank where it resides. the dedicated jtag pins reside in bank 1 of all max ii devices. max ii devices support the jtag instructions shown in table 3?1 . table 3?1. max ii jtag instructions (part 1 of 2) jtag instruction instruction code description sample/preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal devic e operation, and permits an initial data pattern to be output at the device pins. extest (1) 00 0000 1111 allows the external circuitry and board-leve l interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypas s register between the tdi and tdo pins, which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . this register defaults to all 1?s if not specified in the quartus ii software. idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . mii51003-1.3
3?2 core version a.b.c variable altera corporation max ii device handbook, volume 1 june 2005 ieee std. 1149.1 (jtag) boundary scan support highz (1) 00 0000 1011 places the 1-bit bypas s register between the tdi and tdo pins, which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal device operation, wh ile tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypas s register between the tdi and tdo pins, which allows the boundary scan test data to pass synchronously through selected devices to adjacent devices during normal device operation, while holding i/o pins to a state defined by the data in the boundary-scan register. user0 00 0000 1100 this instruction allows the user to define their own scan chain between tdi and tdo in the max ii logic array. this instruction is also used for custom logic and jtag interfaces. user1 00 0000 1110 this instruction allows the user to define their own scan chain between tdi and tdo in the max ii logic array. this instruction is also used for custom logic and jtag interfaces. ieee 1532 instructions (2) ieee 1532 isc instructions used when programming a max ii device via the jtag port. notes to ta b l e 3 ? 1 : (1) highz , clamp , and extest instructions do not disable weak pull-up resistors or bus hold features. (2) these instructions are shown in the 1532 bsdl files, which will be posted on the altera ? web site at www.altera.com when they are available. table 3?1. max ii jtag instructions (part 2 of 2) jtag instruction instruction code description
altera corporation core version a.b.c variable 3?3 june 2005 max ii device handbook, volume 1 jtag & in-system programmability the max ii device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for max ii devices. f for jtag ac characteristics, refer to the chapter on dc & switching characteristics . for more information on jtag bst, see the chapter on ieee 1149.1 (jtag) bo undary-scan testing for max ii devices . jtag block the max ii jtag block feature allo ws you to access the jtag tap and state signals when either the user0 or user1 instruction is issued to the jtag tap. the user0 and user1 instructions bring the jtag boundary scan chain ( tdi ) through the user logic instead of the max ii device?s boundary scan cells. each user instruction allows for one unique user- defined jtag chain into the logic array. table 3?2. max ii boundar y-scan register length device boundary-scan register length epm240 240 epm570 480 epm1270 636 epm2210 816 table 3?3. 32-bit max ii device idcode device binary idcode (32 bits) (1) hex idcode version (4 bits) part number manufacturer identity (11 bits) lsb (1 bit) (2) epm240 0000 0010 0000 1010 0001 000 0110 1110 1 0x020a10dd epm570 0000 0010 0000 1010 0010 000 0110 1110 1 0x020a20dd epm1270 0000 0010 0000 1010 0011 000 0110 1110 1 0x020a30dd epm2210 0000 0010 0000 1010 0100 000 0110 1110 1 0x020a40dd notes to ta b l e 3 ? 2 : (1) the most significant bit (msb) is on the left. (2) the idcode's least significant bit (lsb) is always 1 .
3?4 core version a.b.c variable altera corporation max ii device handbook, volume 1 june 2005 in system programmability parallel flash loader the jtag block ability to interface jt ag to non-jtag devices is ideal for general-purpose flash memory device s (such as intel or fujitsu based devices) that require programming during in-circuit test. the flash memory devices can be used for fpga configuration or be part of system memory. in many cases, the max ii device is already connected to these devices as the configuration control logic between the fpga and the flash device. unlike isp-capable cpld devices, bulk flash devices do not have jtag tap pins or connec tions. for small flash de vices, it is common to use the serial jtag scan chain of a connected device to program the non- jtag flash device. this is slow and inefficient in most cases and impractical for large parallel flash devices. using the max ii device?s jtag block as a parallel flash loader , with the quartus ii software, to program and verify flash contents provides a fast and cost-effective means of in-circuit programming during test. figure 3?1 shows max ii being used as a parallel flash loader. figure 3?1. max ii parallel flash loader notes to figure 3?1 : (1) this block is implemented in les. (2) this function is supported in the quartus ii software. in system programmability max ii devices can be programmed in-system via the industry standard 4-pin ieee std. 1149.1 (jtag) interfac e. in system programmability (isp) offers quick, efficient iterations during design development and parallel flash loader configuration logic flash memory device max ii device dq[7..0] ry/by a[20..0] oe we ce dq[7..0] ry/by a[20..0] oe we ce tdi tms tck tdi_u tdo_u tms_u tck_u shift_u clkdr_u update_u runidle_u user1_u tdo altera fpga conf_done nstatus nce dclk data0 nconfig (1), (2)
altera corporation core version a.b.c variable 3?5 june 2005 max ii device handbook, volume 1 jtag & in-system programmability debugging cycles. the logic, circuitr y, and interconnects in the max ii architecture are configured with flash-based sram configuration elements. these sram elements requir e configuration data to be loaded each time the device is powered. the process of loading the sram data is called configuration. the on-chi p configuration flash memory (cfm) block stores the sram element?s configuration data. the cfm block stores the design?s configuration patt ern in a reprogrammable flash array. during isp, the max ii jtag and isp circuitry prog rams the design pattern into the cfm block?s non-volatile flash array. the max ii jtag and isp controller internally generate the high programming voltages required to program the cfm cells, allowing in- system programming with any of th e recommended operating external voltage supplies (i.e., 3.3 v/2.5 v or 1.8 v for the max iig devices). isp can be performed anytime after v ccint and all v ccio banks have been fully powered and the device has completed the configuration power-up time. by default, during in-syste m programming, the i/o pins are tri- stated and weakly pulled-up to v ccio to eliminate board conflicts. the in- system programming clamp and real-tim e isp feature allows user control of i/o state or behavior during isp. f for more information, refer to ?in-system programming clamp? on page 3?7 and ?real-time isp? on page 3?8 . these devices also offer an isp_done bit that provides safe operation when in-system programmin g is interrupted. this isp_done bit, which is the last bit programmed, prevents all i/o pins from driving until the bit is programmed. ieee 1532 support the jtag circuitry and isp instruction set in max ii devices is compliant to the ieee 1532-2002 programming specification. this provides industry-standard hardware and so ftware for in-system programming among multiple vendor programmable logic devices (plds) in a jtag chain. the max ii 1532 bsdl files will be rele ased on the altera web site when available. jam standard test & programming language (stapl) the jam stapl jedec standard, jesd71, can be used to program max ii devices with in-circuit testers, pcs, or embedded processors. the jam byte code is also supported for max ii devices. these software programming protocols provide a compact embedded solution for programming max ii devices.
3?6 core version a.b.c variable altera corporation max ii device handbook, volume 1 june 2005 in system programmability f for more information, see the chapter on using jam stapl for isp via an embedded processor . programming sequence during in-system programming, 1532 in structions, addresses, and data are shifted into the max ii device through the tdi input pin. data is shifted out through the tdo output pin and compared against the expected data. programming a patte rn into the device requires the following six isp steps. a stand-alone verification of a programmed pattern involves only stag es 1, 2, 5, and 6. thes e steps are automatically executed by third-party programmers, the quartus ? ii software, or the jam stapl and jam byte-code players. 1. enter isp ? the enter isp stage ensures th at the i/o pins transition smoothly from user mode to isp mode. 2. check id ? before any program or verify process, the silicon id is checked. the time required to read this silicon id is relatively small compared to the overall programming time. 3. sector erase ? erasing the device in-system involves shifting in the instruction to erase the device and applying an erase pulse(s). the erase pulse is automati cally generated internal ly by waiting in the run/test/idle state for the specifie d erase pulse time of 500 ms for the cfm block and 500 ms for ea ch sector of the ufm block. 4. program ? programming the device in-system involves shifting in the address, data, and program instruction and generating the program pulse to program the flas h cells. the program pulse is automatically generated internally by waiting in the run/test/idle state for the specified program pulse time of 75 s. this process is repeated for each address in the cfm and ufm block. 5. verify ? verifying a max ii device in-system involves shifting in addresses, applying the verify instruction to generate the read pulse, and shifting out the data for comparison. this process is repeated for each cfm and ufm address. 6. exit isp ? an exit isp stage ensures that the i/o pins transition smoothly from isp mode to user mode.
altera corporation core version a.b.c variable 3?7 june 2005 max ii device handbook, volume 1 jtag & in-system programmability table 3?4 shows the programming times for max ii devices using in- circuit testers to execute the algori thm vectors in hardware. software- based programming tools used with do wnload cables are slightly slower because of data processing and transfer limitations. ufm programming the quartus ii software, with the use of pof, jam, or jbc files, supports programming of the user flash memo ry (ufm) block independent from the logic array design pa ttern stored in the cf m block. this allows updating or reading ufm contents through isp without altering the current logic array design, or vice ve rsa. by default, these programming files and methods will program both the entire flash memory contents, which includes the cfm block an d ufm contents. the stand-alone embedded jam stapl player and jam byte-code player provides action commands for programming or readin g the entire flash memory (ufm and cfm together) or each independently. f for more information, see the chapter on using jam stapl for isp via an embedded processor . in-system programming clamp by default, the ieee 1532 instruction used for entering isp automatically tri-states all i/o pins with weak pull -up resistors for the duration of the isp sequence. however, some systems may require certain pins on max ii devices to maintain a specific dc logic level during an in-field update. for these systems, an opti onal in-system programming clamp instruction exists in max ii circuitr y to control i/o behavior during the isp sequence. the in-system programming clamp instruction enables the device to sample and sustain the valu e on an output pin (an input pin table 3?4. max ii device family programming times description epm240 epm240g epm570 epm570g epm1270 epm1270g epm2210 epm2210g units erase + program (1 mhz) 1.72 2.16 2.90 3.92 sec erase + program (10 mhz) 1.65 1.99 2.58 3.40 sec verify (1 mhz) 0.09 0.17 0.30 0.49 sec verify (10 mhz) 0.01 0.02 0.03 0.05 sec complete program cycle (1 mhz) 1.81 2.33 3.20 4.41 sec complete program cycle (10 mhz) 1.66 2.01 2.61 3.45 sec
3?8 core version a.b.c variable altera corporation max ii device handbook, volume 1 june 2005 in system programmability would remain tri-stated if sampled) or to explicitly set a logic high, logic low, or tri-state value on any pin. se tting these options is controlled on an individual pin basis using the quartus ii software. f for more information, see the chapter on real-time i sp & isp clamp for max ii devices . real-time isp for systems that require more than dc logic level control of i/o pins, the real-time isp feature allows you to update the cfm block with a new design image while the current design continues to operate in the sram logic array and i/o pins. a new programming file is updated into the max ii device without halting the or iginal design?s op eration, saving down-time costs for remote or fiel d upgrades. the updated cfm block configures the new design into the sram upon the next power cycle. it is also possible to execute an immediat e configuration of the sram without a power cycle by using a specific sequence of isp commands. the configuration of sram without a powe r cycle takes a specific amount of time (t config ). during this time, the i/o pi ns are tri-stated and weakly pulled-up to v ccio . design security all max ii devices contain a programm able security bit that controls access to the data programmed into the cfm block. when this bit is programmed, design programming information, stored in the cfm block, cannot be copied or retrieved. this feature provides a high level of design security because programmed data within flash memory cells is invisible. the security bit that controls this functi on, as well as all other programmed data, is reset only when the device is erased. the sram is also invisible and cannot be accessed regardless of the security bit setting. the ufm block data is not protected by the security bit and is accessible through jtag or logic array connections. programming with external hardware max ii devices can be programmed by downloading the information via in-circuit testers, embedded processors, the altera ? byteblastermv?, masterblaster?, byteblaster? ii, and usb-blaster cables. bp microsystems, system general, and other programming hardware manufacturers provide programming support for altera devices. check their web sites for devi ce support information.
altera corporation core version a.b.c variable 4?1 february 2006 preliminary chapter 4. hot socketing & power-on reset in max ii devices hot socketing max ? ii devices offer hot socketing, also known as hot plug-in or hot swap, and power sequencing support. designers can insert or remove a max ii board in a system during oper ation without undesirable effects to the system bus. the hot socketing feat ure removes some of the difficulty designers face when using components on printed circuit boards (pcbs) that contain a mixture of 3.3-, 2.5-, 1.8-, and 1.5-v devices. the max ii device hot socketing feature provides: board or device insertion and removal support for any power-up sequence non-intrusive i/o buffers to system buses during hot insertion max ii hot-socketing specifications max ii devices offer all three of the features required for hot socketing capability listed above without any external components or special design requirements. the following are hot-socketing specifications: the device can be driven before and during power-up or power- down without any damage to the device itself. i/o pins remain tri-stated during power-up. the device does not drive out before or during power-up, thereby affecting other buses in operation. signal pins do not drive the v ccio or v ccint power supplies. external input signals to device i/o pins do not power the device v ccio or v ccint power supplies via internal paths. this is true for all device i/o pins only if v ccint is held at gnd . this is true for a particular i/o bank if the v ccio supply for that bank is held at gnd . devices can be driven before power-up signals can be driven into the max ii device i/o pins and gclk[3..0] pins before or during power-up or power-down without damaging the device. max ii devices support any power-up or power-down sequence (v ccio1 , v ccio2 , v ccio3 , v ccio4 , v ccint ), simplifying system-level design. mii51004-1.4
4?2 core version a.b.c variable altera corporation max ii device handbook, volume 1 february 2006 hot socketing i/o pins remain tri-stated during power-up a device that does not support hot-socketing may interrupt system operation or cause contention by driv ing out before or during power-up. in a hot socketing situation, the max ii device?s output buffers are turned off during system power-up. max ii devices do not drive out until the device attains proper operating conditions and is fully configured. see ?power-on reset circuitry? on page 4?6 for information about turn-on voltages. signal pins do not drive the v ccio or v ccint power supplies max ii devices do not have a current path from i/o pins or gclk[3..0] pins to the v ccio or v ccint pins before or during power-up. a max ii device may be inserted into (or removed from) a system board that was powered up without damaging or interfering with system-board operation. when hot socketing, ma x ii devices may have a minimal effect on the signal integrity of the backplane. ac & dc specifications you can power up or power down the v ccio and v ccint pins in any sequence. during hot socketing, the i/o pin capacitance is less than 8 pf. max ii devices meet the following hot socketing specifications: the hot socketing dc specification is: | i iopin | < 300 a. the hot socketing ac specification is: | i iopin | < 8 ma for 10 ns or less. 1 max ii devices are immune to latch-up when hot socketing. if the tck jtag input pin is driven high during hot-socketing, the current on that pin might exce ed the specifications above. i iopin is the current at any user i/o pin on the device. the ac specification applies when the device is being powered up or powered down. this specification takes into account the pin capacitance but not board trace and external loading capa citance. additional capacitance for trace, connector, and loading must be taken into consideration separately. the peak current duration due to powe r-up transients is 10 ns or less. the dc specification applies when all vcc supplies to the device are stable in the powered-up or powered-down conditions.
altera corporation core version a.b.c variable 4?3 february 2006 max ii device handbook, volume 1 hot socketing & power-on reset in max ii devices hot socketing feature implem entation in max ii devices the hot socketing feature tu rns off (tri-states) the ou tput buffer during the power-up event (either v ccint or v ccio supplies) or power down. the hot-socket circuit generates an internal hotsckt signal when either v ccint or v ccio is below the threshold voltage. the hotsckt signal cuts off the output buffer to make sure that no dc current (except for weak pull-up leaking) leaks through the pin. when v cc ramps up very slowly, v cc may still be relatively low even af ter the power-on reset (por) signal is released and device configuration is complete. each i/o and clock pin has the following circuitry, as shown in figure 4?1 . figure 4?1. hot socketing circuit block diagram for max ii devices the por circuit monitors v ccint and v ccio voltage levels and keeps i/o pins tri-stated until the device has completed its flash memory configuration of the sram logic. the weak pull-up resistor (r) from the i/o pin to v ccio is enabled during download to keep the i/o pins from floating. the 3.3-v tolerance control circuit permits the i/o pins to be driven by 3.3 v before v ccio and/or v ccint are powered, and it prevents the i/o pins from driving out when the device is not fully powered or output enable v ccio hot socket voltage tolerance control power on reset monitor weak pull-up resistor pad input buffer to logic array
4?4 core version a.b.c variable altera corporation max ii device handbook, volume 1 february 2006 hot socketing operational. the hot- socket circuit prevents i/o pins from internally powering v ccio and v ccint when driven by external signals before the device is powered. f for information on 5.0-v tolerance, see the chapter on using max ii devices in multi-voltage systems . figure 4?2 shows a transistor level cross section of the max ii device i/o buffers. this design ensures that th e output buffers do not drive when v ccio is powered before v ccint or if the i/o pad voltage is higher than v ccio . this also applies for sudden voltage spikes during hot insertion. the v pad leakage current charges the 3.3- v tolerant circuit capacitance. figure 4?2. transistor-level diagram of max ii device i/o buffers the cmos output drivers in the i/o pins intrinsically provide electrostatic di scharge (esd) protection. ther e are two cases to consider for esd voltage strikes: positive vo ltage zap and negative voltage zap. a positive esd voltage zap occurs when a positive voltage is present on an i/o pin due to an esd charge even t. this can cause the n+ (drain)/p- substrate junction of the n-channe l drain to break down and the n+ (drain)/p-substrate/n+ (source) intr insic bipolar transistor turns on to discharge esd current from i/o pin to gnd. the dashed line (see figure 4?3 ) shows the esd current discharge path during a positive esd zap. p-substrate p+ p+ n-well n+ vccio n+ n+ p - well ioe signal vpad ioe signal or the larger of vccio or vpad the larger of vccio or vpad ensures 3.3- v tolerance & hot-socket protection
altera corporation core version a.b.c variable 4?5 february 2006 max ii device handbook, volume 1 hot socketing & power-on reset in max ii devices figure 4?3. esd protection during positive voltage zap when the i/o pin receives a negative esd zap at the pin that is less than -0.7 v (0.7 v is the voltage drop across a diode), the intrinsic p-substrate/n+ drain diode is forward biased. hence, the discharge esd current path is from gnd to the i/o pin, as shown in figure 4?4 . i/o i/o gate gate drain drain pmos nmos source source gnd gnd n+ n+ p-substrate g s d
4?6 core version a.b.c variable altera corporation max ii device handbook, volume 1 february 2006 power-on reset circuitry figure 4?4. esd protection during negative voltage zap power-on reset circuitry max ii devices have por circuits to v ccint and v ccio voltage levels during power-up. the por circuit mo nitors these voltages, triggering download from the non-volatile configuration flash memory (cfm) block to the sram logic, maintaining tri-st ate of the i/o pins (with weak pull- up resistors enabled) before and during this process. when the max ii device enters user mode, the por circ uit releases the i/o pins to user functionality and continues to monitor the v ccint voltage level to detect a brown-out condition. power-up characteristics when power is applied to a max ii device, the por circuit monitors v ccint and begins sram download at an approximate voltage of 1.7 v, or 1.55 v for max ii g devices. fr om this voltage reference, sram download and entry into user mode takes 200 to 450 s maximum depending on device density. this period of time is specified as t config in the power-up timing section of chapter 5. dc & swit ching characteristics . entry into user mode is gated by whether all v ccio banks are powered with sufficient operating voltage. if v ccint and v ccio are powered simultaneously, the device enters user mode within the t config i/o i/o gate gate drain drain pmos nmos source source gnd gnd n+ n+ p-substrate g s d
altera corporation core version a.b.c variable 4?7 february 2006 max ii device handbook, volume 1 hot socketing & power-on reset in max ii devices specifications. if v ccio is powered more than t config after v ccint , the device does not enter user mode until 2 s after all v ccio banks are powered. in user mode, the por circuitry continues to monitor the v ccint (but not v ccio ) voltage level to detect a brown-out condition. if there is a v ccint voltage sag at or below 1.4 v during user mode, the por circuit resets the sram and tri-states the i/o pins. once v ccint rises back to approximately 1.7 v (or 1.55 v fo r max ii g devices), the sram download restarts and the devi ce begins to operate after t config time has passed. figure 4?5 shows the voltages for max ii and max ii g device por during power-up into user mode and from user mode to power-down or brown-out.
4?8 core version a.b.c variable altera corporation max ii device handbook, volume 1 february 2006 power-on reset circuitry figure 4?5. power-up characteristics for max ii & max ii g devices notes (1) , (2) notes to figure 4?5 : (1) time scale is relative. (2) figure 4?5 assumes all v ccio banks power simultaneously with the v ccint profile shown. if not, t config stretches out until all v ccio banks are powered. 1 after sram configuration, all registers in the device are cleared and released into user function be fore i/o tri-states are released. to release clears after tri- states are released, use the dev_clrn pin option. to hold the tri-states beyond the power-up configuration time, use the dev_oe pin option. v ccint 3.3 v 1.55 v t config tri-state user mode operation 0 v 1.8 v tri-state 1.4 v v ccint 3.3 v t config tri-state user mode operation 0 v 2.5 v tri-state 1.7 v device resets the sram and tri-states i/o pin s approximate voltage for sram download start max ii device 1.4 v max ii g device device resets the sram and tri-states i/o pins approximate voltage for sram download start
altera corporation core version a.b.c variable 5?1 july 2006 preliminary chapter 5. dc & switching characteristics operating conditions tables 5?1 through 5?12 provide information on absolute maximum ratings, recommended operating conditions, dc electrical characteristics, and other specifications for max ? ii devices. absolute maximum ratings table 5?1 shows the absolute maximum ratings for the max ii device family. table 5?1. max ii device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v ccint internal supply voltage (3) with respect to ground ?0.5 4.6 v v ccio i/o supply voltage ?0.5 4.6 v v i dc input voltage ?0.5 4.6 v i out dc output current, per pin ?25 25 ma t stg storage temperature no bias ?65 150 c t amb ambient temperature under bias ?65 135 c t j junction temperature tqfp and bga packages under bias 135 c notes to ta b l e 5 ? 1 : (1) see the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 5?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) maximum v ccint for max ii devices is 4.6 v. for max iig devices, it is 2.4 v. mii51005-1.7
5?2 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 operating conditions recommended oper ating conditions table 5?2 shows the max ii device family recommended operating conditions. table 5?2. max ii device recommended operating conditions (part 1 of 2) symbol parameter conditions minimum maximum unit v ccint (1) 3.3-v supply voltage for internal logic and isp 3.00 3.60 v 2.5-v supply voltage for internal logic and isp 2.375 2.625 v 1.8-v supply voltage for internal logic and isp (max iig devices) 1.71 1.89 v v ccio (1) supply voltage for i/o buffers, 3.3-v operation 3.00 3.60 v supply voltage for i/o buffers, 2.5-v operation 2.375 2.625 v supply voltage for i/o buffers, 1.8-v operation 1.71 1.89 v supply voltage for i/o buffers, 1.5-v operation 1.425 1.575 v v i input voltage (2) , (3) , (4) ?0.5 4.0 v v o output voltage 0 v ccio v
altera corporation core version a.b.c variable 5?3 july 2006 max ii device handbook, volume 1 dc & switching characteristics programming/erasure specifications table 5?3 shows the max ii device family programming/erasure specifications. t j operating junction temperature commercial range 0 85 c industrial range ?40 100 c extended range (5) ?40 125 c notes to ta b l e 5 ? 2 : (1) max ii device in-system programming and/or ufm program ming via jtag or logic array is not guaranteed outside the recommended operating conditions (i.e., if brown-out occurs in the sy stem during a potential write/program sequence to the ufm, users are recomme nded to read back ufm contents and verify against the intended write data). (2) minimum dc input is ?0.5 v. during transitions, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) during transitions, the inputs may overshoot to the voltages shown in the following table based upon input duty cycle. the dc case is equivalent to 100% duty cycle. for more information on 5.0-v tole rance refer to the chapter on using max ii devices in multi-voltage systems . v in max. duty cycle 4.0 v 100% (dc) 4.1 90% 4.2 50% 4.3 30% 4.4 17% 4.5 10% (4) all pins, including clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (5) for the extended temp erature range of 100 to 125o c, max ii ufm programming (erase/write) is only supported via the jtag interface. ufm programming via the logic a rray interface is not guaranteed in this range. table 5?2. max ii device recommended operating conditions (part 2 of 2) symbol parameter conditions minimum maximum unit table 5?3. max ii device program ming/erasure specifications parameter minimum typical maximum unit erase and reprogram cycles 100 (1) cycles note to ta b l e 5 ? 3 : (1) this specification applies to the user flash memory (ufm) and cfm blocks.
5?4 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 operating conditions dc electrical characteristics table 5?4 shows the max ii device family dc electrical characteristics. table 5?4. max ii device dc electrical characteristics note (1) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (2) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (2) ?10 10 a i ccstandby v ccint supply current (standby) (3) max ii devices 12 ma max iig devices 2 ma v schmitt (4) hysteresis for schmitt trigger input v ccio = 3.3 v 400 mv v ccio = 2.5 v 190 mv i ccpowerup v ccint supply current during power-up (5) max ii devices 55 ma max iig devices 40 ma r pullup value of i/o pin pull-up resistor during user mode and in-system programming v ccio = 3.3 v (6) 525k v ccio = 2.5 v (6) 10 40 k v ccio = 1.8 v (6) 25 60 k v ccio = 1.5 v (6) 45 95 k c io input capacitance for user i/o pin 8pf c gclk input capacitance for dual-purpose gclk /user i/o pin 8pf notes to ta b l e 5 ? 4 : (1) typical values are for t a = 25 c, v ccint = 3.3 or 2.5 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, or 3.3 v. (2) this value is specified for normal device operation. the value may vary during powe r-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (3) v i = ground, no load, no toggling inputs. (4) this value applies to commercial and industrial range devices. for extended temp erature range devices, the v schmitt typical value is 300 mv for v ccio = 3.3 v and 120 mv for v ccio = 2.5 v. (5) this is a peak current value with a maximum duration of t config time. (6) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio .
altera corporation core version a.b.c variable 5?5 july 2006 max ii device handbook, volume 1 dc & switching characteristics output drive characteristics figure 5?1 shows the typical drive streng th characteristics of max ii devices. figure 5?1. output drive characte ristics of max ii devices max ii output drive i oh characteristics (maximum drive strength) 0 10 20 30 40 50 60 70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 voltage (v) typical i o output current (ma) 0 10 20 30 40 50 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 voltage (v) typical i o output current (ma) 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 voltage (v) typical i o output current (ma) 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 voltage (v) typical i o output current (ma) 3.3-v vccio 2.5-v vccio 1. 8 -v vccio 1.5-v vccio 3.3-v vccio 2.5-v vccio 1. 8 -v vccio 1.5-v vccio 3.3-v vccio 2.5-v vccio 1. 8 -v vccio 1.5-v vccio 3.3-v vccio 2.5-v vccio 1. 8 -v vccio 1.5-v vccio (minimum drive strength) max ii output drive i oh characteristics (maximum drive strength) max ii output drive i ol characteristics (minimum drive strength) max ii output drive i ol characteristics
5?6 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 operating conditions i/o standard specifications tables 5?5 through 5?10 show the max ii device family i/o standard specifications. table 5?5. 3.3-v lvttl specifications symbol parameter conditions minimum maximum unit v ccio i/o supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.5 0.8 v v oh high-level output voltage i oh = ?4 ma (1) 2.4 v v ol low-level output voltage i ol = 4 ma (1) 0.45 v table 5?6. 3.3-v lvcmos specifications symbol parameter conditions minimum maximum unit v ccio i/o supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.5 0.8 v v oh high-level output voltage v ccio = 3.0, i oh = -0.1 ma (1) v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma (1) 0.2 v table 5?7. 2.5-v i/o specifications (part 1 of 2) symbol parameter conditions minimum maximum unit v ccio i/o supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.0 v v il low-level input voltage ?0.5 0.7 v
altera corporation core version a.b.c variable 5?7 july 2006 max ii device handbook, volume 1 dc & switching characteristics v oh high-level output voltage i oh = ?0.1 ma (1) 2.1 v i oh = ?1 ma (1) 2.0 v i oh = ?2 ma (1) 1.7 v v ol low-level output voltage i ol = 0.1 ma (1) 0.2 v i ol = 1 ma (1) 0.4 v i ol = 2 ma (1) 0.7 v table 5?8. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio i/o supply voltage 1.71 1.89 v v ih high-level input voltage 0.65 v ccio 2.25 (2) v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (1) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 ma (1) 0.45 v table 5?9. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio i/o supply voltage 1.425 1.575 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 (2) v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (1) 0.75 v ccio v table 5?7. 2.5-v i/o specifications (part 2 of 2) symbol parameter conditions minimum maximum unit
5?8 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 operating conditions bus hold specifications table 5?11 shows the max ii device family bus hold specifications. v ol low-level output voltage i ol = 2 ma (1) 0.25 v ccio v notes to ta b l e s 5 ? 5 through 5?9 : (1) this specification is supported across all the programmable drive strength settings avai lable for this i/o standard, as shown in the max ii architecture chapter ( i/o structure section ) of the max ii device handbook . (2) this maximum v ih reflects the jedec specification. the max ii input buffer can tolerate a v ih maximum of 4.0 as specified by the v i parameter in table 5?2 . table 5?10. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i oh = ?500 a 0.9 v ccio v v ol low-level output voltage i ol = 1.5 ma 0.1 v ccio v table 5?9. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit table 5?11. bus hold specifications (part 1 of 2) parameter conditions v ccio level unit 1.5 v1.8 v2.5 v3.3 v min max min max min max min max low sustaining current v in > v il (maximum)20305070a high sustaining current v in < v ih (minimum) ?20 ?30 -50 ?70 a
altera corporation core version a.b.c variable 5?9 july 2006 max ii device handbook, volume 1 dc & switching characteristics power-up timing table 5?12 shows the power-up timing char acteristics for max ii devices. power consumption designers can use the altera ? web power calculator to estimate the device power. see the chapter on understanding & evalua ting power in max ii devices for more information. low overdrive current 0 v < v in < v ccio 160 200 300 500 a high overdrive current 0 v < v in < v ccio ?160 ?200 ?300 ?500 a table 5?11. bus hold specifications (part 2 of 2) parameter conditions v ccio level unit 1.5 v1.8 v2.5 v3.3 v min max min max min max min max table 5?12. max ii power-up timing symbol parameter device min typ max unit t config (1) the amount of time from when minimum v ccint is reached until the device enters user mode (2) epm240 200 s epm570 300 s epm1270 300 s epm2210 450 s notes to table 5?12 : (1) table 5?12 values apply to commercial and industrial range de vices. for extended temperature range devices, the t config maximum values are as follows: device maximum epm240 300 s epm570 400 s epm1270 400 s epm2210 500 s (2) for more information on por trigge r voltage, refer to the chapter on hot socketing & power- on reset in max ii devices .
5?10 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications timing model & specifications max ii devices timing can be anal yzed with the altera quartus ii software, a variety of popular industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 5?2 . max ii devices have predictable intern al delays that enable the designer to determine the worst-case timing of any design. the software provides timing simulation, point-to-point de lay prediction, and detailed timing analysis for device-wide performance evaluation. figure 5?2. max ii device timing model the timing characteristic s of any signal path can be derived from the timing model and parameters of a pa rticular device. external timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. refer to the chapter on understanding timing in max ii devices for more information. this section describes and specifies the performance, internal, external, and ufm timing specifications. all specifications are representative of worst-case supply voltage and ju nction temperature conditions. preliminary & final timing timing models can have either preliminary or final status. the quartus ? ii software issues an informat ional message during the design compilation if the timing models are preliminary. table 5?13 shows the status of the max ii device timing models. i/o pin i/o input delay t in input global input delay t c4 t r4 output delay t od t xz t zx t local t glob logic element i/o pin t fastio output routing delay user flash memory from adjacent le to adjacent le input routing delay t dl t lut t c lut delay register control delay register delays t co t su t h t pre t clr data-in/lut chain data-out t iodr output & output enable data delay t ioe
altera corporation core version a.b.c variable 5?11 july 2006 max ii device handbook, volume 1 dc & switching characteristics preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual perf ormance of the device under worst- case voltage and junction temperature conditions. table 5?13. max ii device timing model status device preliminary final epm240 v epm570 v epm1270 v epm2210 v
5?12 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications performance table 5?14 shows the max ii device performance for some common designs. all performance values we re obtained with the quartus ii software compilation of megafunctions. these performance values are based on an epm1270 device target. table 5?14. max ii device performance resource used design size & function mode resources used performance unit les ufm blocks -3 speed grade -4 speed grade -5 speed grade le 16-bit counter (1) - 16 0 304.0 247.5 201.1 mhz 64-bit counter (1) - 64 0 201.5 154.8 125.8 mhz 16-to-1 multiplexer - 11 0 6.0 8.0 9.3 ns 32-to-1 multiplexer - 24 0 7.1 9.0 11.4 ns 16-bit xor function - 5 0 5.1 6.6 8.2 ns 16-bit decoder with single address line - 5 0 5.2 6.6 8.2 ns ufm 512 x 16 none 3 1 10.0 10.0 10.0 mhz 512 x 16 spi (2) 37 1 8.0 8.0 8.0 mhz 512 x 8 parallel (3) 73 1 (4) (4) (4) mhz 512 x 16 i 2 c (3) 142 1 100 (5) 100 (5) 100 (5) khz notes to table 5?14 : (1) this design is a binary loadable up counter. (2) this design is configured for read only operation in extended mode. read and write ability increases the number of les used. (3) this design is configured for read-only operation. read and write ability increases the number of les used. (4) this design is asynchronous. (5) the i 2 c megafunction is verified in hardware up to 100-khz serial clock line (scl) rate.
altera corporation core version a.b.c variable 5?13 july 2006 max ii device handbook, volume 1 dc & switching characteristics internal timing parameters internal timing parame ters are specified on a speed grade basis independent of device density. tables 5?15 through 5?22 describe the max ii device internal timing microp arameters for logic elements (les), input/output elements (ioes), ufm structures, and multitrack tm interconnects. f for more explanations and descript ions on each internal timing microparameters symbol, refer to the chapter on understanding timing in max ii devices . table 5?15. le internal timing microparameters symbol parameter -3 speed grade -4 speed grade -5 speed grade unit min max min max min max t lut le combinational lut delay 571 742 914 ps t clr le register clear delay 238 309 381 ps t pre le register preset delay 238 309 381 ps t su le register setup time before clock 208 271 333 ps t h le register hold time after clock 0 0 0 ps t co le register clock-to- output delay 235 305 376 ps t clkhl minimum clock high or low time 166 216 266 ps t c register control delay 857 1,114 1,372 ps table 5?16. ioe internal timing microparameters (part 1 of 2) symbol parameter -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax t fastio data output delay from adjacent le to i/o block 159 207 254 ps t in i/o input pad and buffer delay 708 920 1,132 ps
5?14 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications tables 5?17 and 5?18 show the adder delays for t od and t zx microparameters when using an i/o standard other than 3.3-v lvttl with 16 ma drive strength. t glob (1) i/o input pad and buffer delay use as global signal pin 1,519 1,974 2,430 ps t ioe internally generated output enable delay 354 374 460 ps t dl input routing delay 224 291 358 ps t od (2) output delay buffer and pad delay 1,064 1,383 1,702 ps t xz (3) output buffer disable delay 756 982 1,209 ps t zx (4) output buffer enable delay 1,003 1,303 1,604 ps notes to table 5?16 : (1) delay numbers for t glob differ for each device density and sp eed grade. the delay numbers shown in table 5?16 are based on an epm240 device target. (2) refer to tab le 5?29 and table 5?31 for delay adders associated with differe nt i/o standards, drive strengths, and slew rates. (3) refer to table 5?19 and table 5?20 for t xz delay adders associated with differ ent i/o standards, drive strengths, and slew rates. (4) refer to table 5?17 and table 5?18 for t zx delay adders associated with differ ent i/o standards, drive strengths, and slew rates. table 5?16. ioe internal timing microparameters (part 2 of 2) symbol parameter -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax table 5?17. t zx ioe microparameter adders for fast slew rate (part 1 of 2) standard -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax 3.3-v lvcmos 8 ma 0 0 0 ps 4 ma 28 37 45 ps 3.3-v lvttl 16 ma 0 0 0 ps 8 ma 28 37 45 ps 2.5-v lvttl 14 ma 14 19 23 ps 7 ma 314 409 503 ps
altera corporation core version a.b.c variable 5?15 july 2006 max ii device handbook, volume 1 dc & switching characteristics 1.8-v lvttl 6 ma 450 585 720 ps 3 ma 1,443 1,876 2,309 ps 1.5-v lvttl 4 ma 1,118 1,454 1,789 ps 2 ma 2,410 3,133 3,856 ps 3.3-v pci 20 ma 19 25 31 ps table 5?18. t zx ioe microparameter adders for slow slew rate standard -3 speed grade -4 speed grade -5 speed grade unit min max min max min max 3.3-v lvcmos 8 ma 6,350 6,050 5,749 ps 4 ma 9,383 9,083 8,782 ps 3.3-v lvttl 16 ma 6,350 6,050 5,749 ps 8 ma 9,383 9,083 8,782 ps 2.5-v lvttl 14 ma 10,412 10,112 9,811 ps 7 ma 13,613 13,313 13,012 ps 3.3-v pci 20 ma ?75 ?97 ?120 ps table 5?19. t xz ioe microparameter adders for fast slew rate (part 1 of 2) standard -3 speed grade -4 speed grade -5 speed grade unit min max min max min max 3.3-v lvcmos 8 ma 0 0 0 ps 4 ma ?56 ?72 ?89 ps 3.3-v lvttl 16 ma 0 0 0 ps 8 ma ?56 ?72 ?89 ps 2.5-v lvttl 14 ma ?3 ?4 ?5 ps 7 ma ?47 ?61 ?75 ps 1.8-v lvttl 6 ma 119 155 191 ps 3 ma 207 269 331 ps table 5?17. t zx ioe microparameter adders for fast slew rate (part 2 of 2) standard -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax
5?16 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications 1.5-v lvttl 4 ma 606 788 970 ps 2 ma 673 875 1,077 ps 3.3-v pci 20 ma 71 93 114 ps table 5?20. t xz ioe microparameter adders for slow slew rate standard -3 speed grade -4 speed grade -5 speed grade unit min max min max min max 3.3-v lvcmos 8 ma 206 ?20 ?247 ps 4 ma 891 665 438 ps 3.3-v lvttl 16 ma 206 ?20 ?247 ps 8 ma 891 665 438 ps 2.5-v lvttl 14 ma 222 ?4 ?231 ps 7 ma 943 717 490 ps 3.3-v pci 20 ma 161 210 258 ps table 5?21. ufm block internal timing microparameters (part 1 of 3) symbol parameter -3 speed grade -4 speed grade -5 speed grade unit min max min max min max t aclk address register clock period 100 100 100 ns t asu address register shift signal setup to address register clock 20 20 20 ns t ah address register shift signal hold to address register clock 20 20 20 ns t ads address register data in setup to address register clock 20 20 20 ns table 5?19. t xz ioe microparameter adders for fast slew rate (part 2 of 2) standard -3 speed grade -4 speed grade -5 speed grade unit min max min max min max
altera corporation core version a.b.c variable 5?17 july 2006 max ii device handbook, volume 1 dc & switching characteristics t adh address register data in hold from address register clock 20 20 20 ns t dclk data register clock period 100 100 100 ns t dss data register shift signal setup to data register clock 60 60 60 ns t dsh data register shift signal hold from data register clock 20 20 20 ns t dds data register data in setup to data register clock 20 20 20 ns t ddh data register data in hold from data register clock 20 20 20 ns t dp program signal to data clock hold time 000ns t pb maximum delay between program rising edge to ufm busy signal rising edge 960 960 960 ns t bp minimum delay allowed from ufm busy signal going low to program signal going low 20 20 20 ns t ppmx maximum length of busy pulse during a program 100 100 100 s t ae minimum erase signal to address clock hold time 000 ns t eb maximum delay between the erase rising edge to the ufm busy signal rising edge 960 960 960 ns table 5?21. ufm block internal timing microparameters (part 2 of 3) symbol parameter -3 speed grade -4 speed grade -5 speed grade unit min max min max min max
5?18 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications t be minimum delay allowed from the ufm busy signal going low to erase signal going low 20 20 20 ns t epmx maximum length of busy pulse during an erase 500 500 500 ms t dco delay from data register clock to data register output 555ns t oe delay from data register clock to data register output 180 180 180 ns t ra maximum read access time 65 65 65 ns t oscs maximum delay between the osc_ena rising edge to the erase/program signal rising edge 250 250 250 ns t osch minimum delay allowed from the erase/program signal going low to osc_ena signal going low 250 250 250 ns table 5?21. ufm block internal timing microparameters (part 3 of 3) symbol parameter -3 speed grade -4 speed grade -5 speed grade unit min max min max min max
altera corporation core version a.b.c variable 5?19 july 2006 max ii device handbook, volume 1 dc & switching characteristics figures 5?3 through 5?5 show the read, program, and erase waveforms for ufm block timing parameters shown in table 5?21 . figure 5?3. ufm read waveforms figure 5?4. ufm program waveforms t dco t dclk t dss t dsh t adh t ads t asu t aclk t ah arshft arclk ardin drshft drclk drdin drdout program erase busy 16 data bits 9 address bits osc_ena t ads t asu t aclk t adh t ah t dds t dclk t dss t dsh t ddh t pb t bp t ppmx t oscs t osch arshft arclk ardin drshft drclk drdin drdout program erase busy 16 data bits 9 address bits osc_ena
5?20 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications figure 5?5. ufm erase waveforms external timing parameters external timing parameters are specified by device density and speed grade. all external i/o timing para meters shown are for the 3.3-v lvttl i/o standard with the maximum drive strength and fast slew rate. for external i/o timing using standards other than lvttl or for different drive strengths, use the i/o standard input and output delay adders in tables 5?27 through 5?31 . arshft arclk ardin drshft drclk drdin drdout program erase busy 9 address bits t asu t aclk t ah t adh t ads t eb t epmx t oscs t osch osc_ena t be table 5?22. routing delay internal timing microparameters routing -3 speed grade -4 speed grade -5 speed grade unit min max min max min max t c4 429 556 687 ps t r4 326 423 521 ps t local 330 429 529 ps
altera corporation core version a.b.c variable 5?21 july 2006 max ii device handbook, volume 1 dc & switching characteristics table 5?23 shows the external i/o timing parameters for epm240 devices. table 5?23. epm240 global clock ex ternal i/o timing parameters symbol parameter condition -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax t pd1 worst case pin to pin delay through 1 look-up table (lut) 10 pf 4.7 6.1 7.5 ns t pd2 best case pin to pin delay through 1lut 10 pf 3.7 4.8 5.9 ns t su global clock setup time 1.7 2.2 2.7 ns t h global clock hold time 0.0 0.0 0.0 ns t co global clock to output delay 10 pf 2.0 4.3 2.0 5.6 2.0 6.9 ns t ch global clock high time 166 216 266 ps t cl global clock low time 166 216 266 ps t cnt minimum global clock period for 16-bit counter 3.3 4.0 5.0 ns f cnt maximum global clock frequency for 16-bit counter 304.0 (1) 247.5 201.1 mhz note to table 5?23 : (1) the maximum frequency is limited by the i/o standard on the clock input pi n. the 16-bit counter critical delay performs faster than this global clock input pin maximum frequency.
5?22 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications table 5?24 shows the external i/o timing parameters for epm570 devices. table 5?24. epm570 global clock ex ternal i/o timing parameters symbol parameter condition -3 speed grade -4 speed grade -5 speed grade unit min max min max min max t pd1 worst case pin to pin delay through 1 look-up table (lut) 10 pf 5.4 7.0 8.7 ns t pd2 best case pin to pin delay through 1 lut 10 pf 3.7 4.8 5.9 ns t su global clock setup time 1.2 1.5 1.9 ns t h global clock hold time 0.0 0.0 0.0 ns t co global clock to output delay 10 pf 2.0 4.5 2.0 5.8 2.0 7.1 ns t ch global clock high time 166 216 266 ps t cl global clock low time 166 216 266 ps t cnt minimum global clock period for 16-bit counter 3.3 4.0 5.0 ns f cnt maximum global clock frequency for 16-bit counter 304.0 (1) 247.5 201.1 mhz note to table 5?24 : (1) the maximum frequency is limited by the i/o standard on the clock input pi n. the 16-bit counter critical delay performs faster than this global clock input pin maximum frequency.
altera corporation core version a.b.c variable 5?23 july 2006 max ii device handbook, volume 1 dc & switching characteristics table 5?25 shows the external i/o timing parameters for epm1270 devices table 5?25. epm1270 global clock ex ternal i/o timing parameters symbol parameter condition -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax t pd1 worst case pin to pin delay through 1 look-up table (lut) 10 pf 6.2 8.1 10.0 ns t pd2 best case pin to pin delay through 1 lut 10 pf 3.7 4.8 5.9 ns t su global clock setup time 1.2 1.5 1.9 ns t h global clock hold time 0.0 0.0 0.0 ns t co global clock to output delay 10 pf 2.0 4.6 2.0 5.9 2.0 7.3 ns t ch global clock high time 166 216 266 ps t cl global clock low time 166 216 266 ps t cnt minimum global clock period for 16-bit counter 3.3 4.0 5.0 ns f cnt maximum global clock frequency for 16-bit counter 304.0 (1) 247.5 201.1 mhz note to table 5?25 : (1) the maximum frequency is limited by the i/o standard on the clock input pi n. the 16-bit counter critical delay performs faster than this global clock input pin maximum frequency.
5?24 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications table 5?26 shows the external i/o timing parameters for epm2210 devices. table 5?26. epm2210 global clock ex ternal i/o timing parameters symbol parameter condition -3 speed grade -4 speed grade -5 speed grade unit min max min max min max t pd1 worst case pin to pin delay through 1 look-up table (lut) 10 pf 7.0 9.1 11.2 ns t pd2 best case pin to pin delay through 1 lut 10 pf 3.7 4.8 5.9 ns t su global clock setup time 1.2 1.5 1.9 ns t h global clock hold time 0.0 0.0 0.0 ns t co global clock to output delay 10 pf 2.0 4.6 2.0 6.0 2.0 7.4 ns t ch global clock high time 166 216 266 ps t cl global clock low time 166 216 266 ps t cnt minimum global clock period for 16-bit counter 3.3 4.0 5.0 ns f cnt maximum global clock frequency for 16-bit counter 304.0 (1) 247.5 201.1 mhz note to table 5?26 : (1) the maximum frequency is limited by the i/o standard on the clock input pi n. the 16-bit counter critical delay performs faster than this global clock input pin maximum frequency.
altera corporation core version a.b.c variable 5?25 july 2006 max ii device handbook, volume 1 dc & switching characteristics external timing i/o delay adders i/o delay timing parameters for i/o standard input an d output adders and input delays are specified by speed grade independent of device density. tables 5?27 through 5?31 show the adder delays as sociated with i/o pins for all packages. if an i/o standard other than 3.3-v lvttl is selected, add the input delay adder to the external t su timing parameters shown in tables 5?23 through 5?26 . if an i/o standard other than 3.3-v lvttl with 16 ma drive strength and fast slew rate is selected, add the output delay adder to the external t co and t pd shown in tables 5?23 through 5?26 . table 5?27. external timing input delay adders standard -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax 3.3-v lvttl without schmitt trigger 000ps with schmitt trigger 334 434 535 ps 3.3-v lvcmos without schmitt trigger 000ps with schmitt trigger 334 434 535 ps 2.5-v lvttl without schmitt trigger 23 30 37 ps with schmitt trigger 339 441 543 ps 1.8-v lvttl without schmitt trigger 291 378 466 ps 1.5-v lvttl without schmitt trigger 681 885 1,090 ps 3.3-v pci without schmitt trigger 000ps
5?26 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications table 5?28. external timing input delay t glob adders for gclk pins standard -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax 3.3-v lvttl without schmitt trigger 000ps with schmitt trigger 308 400 493 ps 3.3-v lvcmos without schmitt trigger 000ps with schmitt trigger 308 400 493 ps 2.5-v lvttl without schmitt trigger 21 27 33 ps with schmitt trigger 423 550 677 ps 1.8-v lvttl without schmitt trigger 353 459 565 ps 1.5-v lvttl without schmitt trigger 855 1,111 1,368 ps 3.3-v pci without schmitt trigger 679ps table 5?29. external timing output delay & t od adders for fast slew rate standard -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax 3.3-v lvttl 16 ma 0 0 0 ps 8 ma 65 84 104 ps 3.3-v lvcmos 8 ma 0 0 0 ps 4 ma 65 84 104 ps 2.5-v lvttl 14 ma 122 158 195 ps 7 ma 193 251 309 ps 1.8-v lvttl 6 ma 568 738 909 ps 3 ma 654 850 1,046 ps 1.5-v lvttl 4 ma 1,059 1,376 1,694 ps 2 ma 1,167 1,517 1,867 ps 3.3-v pci 20 ma 3 4 5 ps
altera corporation core version a.b.c variable 5?27 july 2006 max ii device handbook, volume 1 dc & switching characteristics maximum input & output clock rates tables 5?32 and 5?33 show the maximum input and output clock rates for standard i/o pins in max ii devices. table 5?30. external timing output delay & t od adders for slow slew rate standard -3 speed grade -4 speed grade -5 speed grade unit minmaxminmaxminmax 3.3-v lvttl 16 ma 7,064 6,745 6,426 ps 8 ma 7,946 7,627 7,308 ps 3.3-v lvcmos 8 ma 7,064 6,745 6,426 ps 4 ma 7,946 7,627 7,308 ps 2.5-v lvttl 14 ma 10,434 10,115 9,796 ps 7 ma 11,548 11,229 10,910 ps 1.8-v lvttl / lv c m o s 6 ma 22,927 22,608 22,289 ps 3 ma 24,731 24,412 24,093 ps 1.5-v lvcmos 4 ma 38,723 38,404 38,085 ps 2 ma 41,330 41,011 40,692 ps 3.3-v pci 20 ma 261 339 418 ps table 5?31. max ii ioe programmable delays parameter -3 speed grade -4 speed grade -5 speed grade unit min max min max min max increase_input_delay_to_internal_cells=on 1,225 1,592 1,960 ps increase_input_delay_to_internal_cells=off 89 115 142 ps table 5?32. max ii maximum input clock rate for i/o (part 1 of 2) standard -3 speed grade -4 speed grade -5 speed grade unit 3.3-v lvttl without schmitt trigger 304 304 304 mhz with schmitt trigger 250 250 250 mhz 3.3-v lvcmos without schmitt trigger 304 304 304 mhz with schmitt trigger 250 250 250 mhz
5?28 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications 2.5-v lvttl without schmitt trigger 220 220 220 mhz with schmitt trigger 188 188 188 mhz 2.5-v lvcmos without schmitt trigger 220 220 220 mhz with schmitt trigger 188 188 188 mhz 1.8-v lvttl without schmitt trigger 200 200 200 mhz 1.8-v lvcmos without schmitt trigger 200 200 200 mhz 1.5-v lvcmos without schmitt trigger 150 150 150 mhz 3.3-v pci without schmitt trigger 304 304 304 mhz table 5?33. max ii maximum output clock rate for i/o standard -3 speed grade -4 speed grade -5 speed grade unit 3.3-v lvttl 304 304 304 mhz 3.3-v lvcmos 304 304 304 mhz 2.5-v lvttl 220 220 220 mhz 2.5-v lvcmos 220 220 220 mhz 1.8-v lvttl 200 200 200 mhz 1.8-v lvcmos 200 200 200 mhz 1.5-v lvcmos 150 150 150 mhz 3.3-v pci 304 304 304 mhz table 5?32. max ii maximum input clock rate for i/o (part 2 of 2) standard -3 speed grade -4 speed grade -5 speed grade unit
altera corporation core version a.b.c variable 5?29 july 2006 max ii device handbook, volume 1 dc & switching characteristics jtag timing specifications figure 5?6 shows the timing waveforms for the jtag signals. figure 5?6. max ii jtag timing waveforms table 5?34 shows the jtag timing parameters and values for max ii devices. tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz table 5?34. max ii jtag timing parameters (part 1 of 2) symbol parameter min max unit t jcp (1) tck clock period for v ccio1 = 3.3 v 55.5 ns tck clock period for v ccio1 = 2.5 v 62.5 ns tck clock period for v ccio1 = 1.8 v 100 ns tck clock period for v ccio1 = 1.5 v 143 ns t jch tck clock high time 20 ns t jcl tck clock low time 20 ns t jpsu jtag port setup time (2) 8ns t jph jtag port hold time 10 ns
5?30 core version a.b.c variable altera corporation max ii device handbook, volume 1 july 2006 timing model & specifications t jpco jtag port clock to output (2) 15 ns t jpzx jtag port high impedance to valid output (2) 15 ns t jpxz jtag port valid output to high impedance (2) 15 ns t jssu capture register setup time 8ns t jsh capture register hold time 10 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns notes to table 5?34 : (1) minimum clock period specified for 10 pf load on the tdo pin. larger loads on tdo will degrade the maximum tck frequency. (2) this specification is shown for 3.3-v lvttl/lvcmos an d 2.5-v lvttl/lvcmos operat ion of the jtag pins. for 1.8-v lvttl/lvcmos an d 1.5-v lvcmos, the t jpsu minimum is 6 ns and t jpco , t jpzx , and t jpxz are maximum values at 35 ns. table 5?34. max ii jtag timing parameters (part 2 of 2) symbol parameter min max unit
altera corporation core version a.b.c variable 6?1 june 2005 preliminary chapter 6. reference & ordering information software max ? ii devices are supported by the altera ? quartus ? ii design software with new, optional max+plus ? ii look and feel, which provides hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced timing analysis, and device programming. see the design software selector guide for more details on the quartus ii software features. the quartus ii software support s the windows xp/2000/nt, sun solaris, linux red hat v8.0, and hp -ux operating systems. it also supports seamless integr ation with industry-leading eda tools through the nativelink ? interface. device pin-outs printed device pin-outs for max ii devi ces will be released on the altera web site ( www.altera.com ) and in the max ii device handbook when they are available. ordering information figure 6?1 describes the ordering codes for max ii devices. for more information on a specific pack age, refer to the chapter on package information . mii51006-1.1
6?2 core version a.b.c variable altera corporation max ii device handbook, volume 1 june 2005 ordering information figure 6?1. max ii device pa ckaging ordering information package type t: f: thin quad flat pack (tqfp) fineline bga ? 240: 570: 1270: 2210: speed grade family signature epm: max ii operating temperature pin count device type 240 logic elements 570 logic elements 1,270 logic elements 2,210 logic elements es: optional suffix engineering sample indicates specific device options or shipment method 3, 4, or 5 with 3 being the fastest number of pins for a particular package c: i: commercial temperature (t j = 0 ? c to 85 ? c) industrial temperature (t j = -40 ? c to 100 ? c) epm 240 g t 100 c 3 es product-line suffix g: blank: indicates device core voltage 1.8-v v ccint device 2.5-v or 3.3-v v ccint device n: lead-free packaging

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